base_set_assoc.hh revision 13222:0dbcc7d7d66f 
1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
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26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "mem/cache/base.hh"
58#include "mem/cache/blk.hh"
59#include "mem/cache/replacement_policies/base.hh"
60#include "mem/cache/tags/base.hh"
61#include "mem/cache/tags/indexing_policies/base.hh"
62#include "params/BaseSetAssoc.hh"
63
64/**
65 * A basic cache tag store.
66 * @sa  \ref gem5MemorySystem "gem5 Memory System"
67 *
68 * The BaseSetAssoc placement policy divides the cache into s sets of w
69 * cache lines (ways).
70 */
71class BaseSetAssoc : public BaseTags
72{
73  protected:
74    /** The allocatable associativity of the cache (alloc mask). */
75    unsigned allocAssoc;
76
77    /** The cache blocks. */
78    std::vector<CacheBlk> blks;
79
80    /** Whether tags and data are accessed sequentially. */
81    const bool sequentialAccess;
82
83    /** Replacement policy */
84    BaseReplacementPolicy *replacementPolicy;
85
86  public:
87    /** Convenience typedef. */
88     typedef BaseSetAssocParams Params;
89
90    /**
91     * Construct and initialize this tag store.
92     */
93    BaseSetAssoc(const Params *p);
94
95    /**
96     * Destructor
97     */
98    virtual ~BaseSetAssoc() {};
99
100    /**
101     * Initialize blocks and set the parent cache back pointer.
102     *
103     * @param _cache Pointer to parent cache.
104     */
105    void init(BaseCache *_cache) override;
106
107    /**
108     * This function updates the tags when a block is invalidated. It also
109     * updates the replacement data.
110     *
111     * @param blk The block to invalidate.
112     */
113    void invalidate(CacheBlk *blk) override;
114
115    /**
116     * Access block and update replacement data. May not succeed, in which case
117     * nullptr is returned. This has all the implications of a cache
118     * access and should only be used as such. Returns the access latency as a
119     * side effect.
120     * @param addr The address to find.
121     * @param is_secure True if the target memory space is secure.
122     * @param lat The access latency.
123     * @return Pointer to the cache block if found.
124     */
125    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
126    {
127        CacheBlk *blk = findBlock(addr, is_secure);
128
129        // Access all tags in parallel, hence one in each way.  The data side
130        // either accesses all blocks in parallel, or one block sequentially on
131        // a hit.  Sequential access with a miss doesn't access data.
132        tagAccesses += allocAssoc;
133        if (sequentialAccess) {
134            if (blk != nullptr) {
135                dataAccesses += 1;
136            }
137        } else {
138            dataAccesses += allocAssoc;
139        }
140
141        if (blk != nullptr) {
142            // If a cache hit
143            lat = accessLatency;
144            // Check if the block to be accessed is available. If not,
145            // apply the accessLatency on top of block->whenReady.
146            if (blk->whenReady > curTick() &&
147                cache->ticksToCycles(blk->whenReady - curTick()) >
148                accessLatency) {
149                lat = cache->ticksToCycles(blk->whenReady - curTick()) +
150                accessLatency;
151            }
152
153            // Update number of references to accessed block
154            blk->refCount++;
155
156            // Update replacement data of accessed block
157            replacementPolicy->touch(blk->replacementData);
158        } else {
159            // If a cache miss
160            lat = lookupLatency;
161        }
162
163        return blk;
164    }
165
166    /**
167     * Find replacement victim based on address. The list of evicted blocks
168     * only contains the victim.
169     *
170     * @param addr Address to find a victim for.
171     * @param is_secure True if the target memory space is secure.
172     * @param evict_blks Cache blocks to be evicted.
173     * @return Cache block to be replaced.
174     */
175    CacheBlk* findVictim(Addr addr, const bool is_secure,
176                         std::vector<CacheBlk*>& evict_blks) const override
177    {
178        // Get possible entries to be victimized
179        const std::vector<ReplaceableEntry*> entries =
180            indexingPolicy->getPossibleEntries(addr);
181
182        // Choose replacement victim from replacement candidates
183        CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
184                                entries));
185
186        // There is only one eviction for this replacement
187        evict_blks.push_back(victim);
188
189        return victim;
190    }
191
192    /**
193     * Insert the new block into the cache and update replacement data.
194     *
195     * @param addr Address of the block.
196     * @param is_secure Whether the block is in secure space or not.
197     * @param src_master_ID The source requestor ID.
198     * @param task_ID The new task ID.
199     * @param blk The block to update.
200     */
201    void insertBlock(const Addr addr, const bool is_secure,
202                     const int src_master_ID, const uint32_t task_ID,
203                     CacheBlk *blk) override
204    {
205        // Insert block
206        BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk);
207
208        // Increment tag counter
209        tagsInUse++;
210
211        // Update replacement policy
212        replacementPolicy->reset(blk->replacementData);
213    }
214
215    /**
216     * Limit the allocation for the cache ways.
217     * @param ways The maximum number of ways available for replacement.
218     */
219    virtual void setWayAllocationMax(int ways) override
220    {
221        fatal_if(ways < 1, "Allocation limit must be greater than zero");
222        allocAssoc = ways;
223    }
224
225    /**
226     * Get the way allocation mask limit.
227     * @return The maximum number of ways available for replacement.
228     */
229    virtual int getWayAllocationMax() const override
230    {
231        return allocAssoc;
232    }
233
234    /**
235     * Regenerate the block address from the tag and indexing location.
236     *
237     * @param block The block.
238     * @return the block address.
239     */
240    Addr regenerateBlkAddr(const CacheBlk* blk) const override
241    {
242        return indexingPolicy->regenerateAddr(blk->tag, blk);
243    }
244
245    void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
246        for (CacheBlk& blk : blks) {
247            visitor(blk);
248        }
249    }
250
251    bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
252        for (CacheBlk& blk : blks) {
253            if (visitor(blk)) {
254                return true;
255            }
256        }
257        return false;
258    }
259};
260
261#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
262