base_set_assoc.hh revision 13215:82cdb8db4643
13898Ssaidi@eecs.umich.edu/* 22934Sktlim@umich.edu * Copyright (c) 2012-2014,2017 ARM Limited 32934Sktlim@umich.edu * All rights reserved. 42934Sktlim@umich.edu * 52934Sktlim@umich.edu * The license below extends only to copyright in the software and shall 62934Sktlim@umich.edu * not be construed as granting a license to any other intellectual 72934Sktlim@umich.edu * property including but not limited to intellectual property relating 82934Sktlim@umich.edu * to a hardware implementation of the functionality of the software 92934Sktlim@umich.edu * licensed hereunder. You may use the software subject to the license 102934Sktlim@umich.edu * terms below provided that you ensure that this notice is replicated 112934Sktlim@umich.edu * unmodified and in its entirety in all distributions of the software, 122934Sktlim@umich.edu * modified or unmodified, in source code or in binary form. 132934Sktlim@umich.edu * 142934Sktlim@umich.edu * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 152934Sktlim@umich.edu * All rights reserved. 162934Sktlim@umich.edu * 172934Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu * this software without specific prior written permission. 272934Sktlim@umich.edu * 282934Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302969Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322995Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu * 402934Sktlim@umich.edu * Authors: Erik Hallnor 412934Sktlim@umich.edu */ 422934Sktlim@umich.edu 432934Sktlim@umich.edu/** 442934Sktlim@umich.edu * @file 452934Sktlim@umich.edu * Declaration of a base set associative tag store. 462934Sktlim@umich.edu */ 472934Sktlim@umich.edu 483005Sstever@eecs.umich.edu#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 492934Sktlim@umich.edu#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 503005Sstever@eecs.umich.edu 513005Sstever@eecs.umich.edu#include <functional> 523304Sstever@eecs.umich.edu#include <string> 532995Ssaidi@eecs.umich.edu#include <vector> 542934Sktlim@umich.edu 552934Sktlim@umich.edu#include "base/logging.hh" 564444Ssaidi@eecs.umich.edu#include "base/types.hh" 572995Ssaidi@eecs.umich.edu#include "debug/CacheRepl.hh" 582934Sktlim@umich.edu#include "mem/cache/base.hh" 592934Sktlim@umich.edu#include "mem/cache/blk.hh" 602934Sktlim@umich.edu#include "mem/cache/replacement_policies/base.hh" 612934Sktlim@umich.edu#include "mem/cache/tags/base.hh" 622934Sktlim@umich.edu#include "mem/cache/tags/cacheset.hh" 632995Ssaidi@eecs.umich.edu#include "params/BaseSetAssoc.hh" 642934Sktlim@umich.edu 652934Sktlim@umich.edu/** 662934Sktlim@umich.edu * A BaseSetAssoc cache tag store. 672934Sktlim@umich.edu * @sa \ref gem5MemorySystem "gem5 Memory System" 682934Sktlim@umich.edu * 692995Ssaidi@eecs.umich.edu * The BaseSetAssoc placement policy divides the cache into s sets of w 702934Sktlim@umich.edu * cache lines (ways). A cache line is mapped onto a set, and can be placed 712934Sktlim@umich.edu * into any of the ways of this set. 722953Sktlim@umich.edu */ 734094Sbinkertn@umich.educlass BaseSetAssoc : public BaseTags 742934Sktlim@umich.edu{ 753449Shsul@eecs.umich.edu public: 762934Sktlim@umich.edu /** Typedef the block type used in this tag store. */ 772934Sktlim@umich.edu typedef CacheBlk BlkType; 782934Sktlim@umich.edu /** Typedef the set type used in this tag store. */ 792934Sktlim@umich.edu typedef CacheSet<CacheBlk> SetType; 802934Sktlim@umich.edu 813584Ssaidi@eecs.umich.edu protected: 824486Sbinkertn@umich.edu /** The associativity of the cache. */ 834486Sbinkertn@umich.edu const unsigned assoc; 844486Sbinkertn@umich.edu /** The allocatable associativity of the cache (alloc mask). */ 854486Sbinkertn@umich.edu unsigned allocAssoc; 864486Sbinkertn@umich.edu 874486Sbinkertn@umich.edu /** The cache blocks. */ 884486Sbinkertn@umich.edu std::vector<BlkType> blks; 893584Ssaidi@eecs.umich.edu 903584Ssaidi@eecs.umich.edu /** The number of sets in the cache. */ 913584Ssaidi@eecs.umich.edu const unsigned numSets; 923584Ssaidi@eecs.umich.edu 933584Ssaidi@eecs.umich.edu /** Whether tags and data are accessed sequentially. */ 943743Sgblack@eecs.umich.edu const bool sequentialAccess; 953584Ssaidi@eecs.umich.edu 964444Ssaidi@eecs.umich.edu /** The cache sets. */ 973743Sgblack@eecs.umich.edu std::vector<SetType> sets; 984104Ssaidi@eecs.umich.edu 993743Sgblack@eecs.umich.edu /** The amount to shift the address to get the set. */ 1003823Ssaidi@eecs.umich.edu int setShift; 1013814Ssaidi@eecs.umich.edu /** The amount to shift the address to get the tag. */ 1023743Sgblack@eecs.umich.edu int tagShift; 1033743Sgblack@eecs.umich.edu /** Mask out all bits that aren't part of the set index. */ 1043584Ssaidi@eecs.umich.edu unsigned setMask; 1053814Ssaidi@eecs.umich.edu 1063584Ssaidi@eecs.umich.edu /** Replacement policy */ 1073745Sgblack@eecs.umich.edu BaseReplacementPolicy *replacementPolicy; 1083745Sgblack@eecs.umich.edu 1093745Sgblack@eecs.umich.edu public: 1103584Ssaidi@eecs.umich.edu /** Convenience typedef. */ 1113898Ssaidi@eecs.umich.edu typedef BaseSetAssocParams Params; 1123898Ssaidi@eecs.umich.edu 1133898Ssaidi@eecs.umich.edu /** 1144103Ssaidi@eecs.umich.edu * Construct and initialize this tag store. 1154103Ssaidi@eecs.umich.edu */ 1164103Ssaidi@eecs.umich.edu BaseSetAssoc(const Params *p); 1173745Sgblack@eecs.umich.edu 1183745Sgblack@eecs.umich.edu /** 1193745Sgblack@eecs.umich.edu * Destructor 1203584Ssaidi@eecs.umich.edu */ 1213584Ssaidi@eecs.umich.edu virtual ~BaseSetAssoc() {}; 1223584Ssaidi@eecs.umich.edu 1233584Ssaidi@eecs.umich.edu /** 1243025Ssaidi@eecs.umich.edu * This function updates the tags when a block is invalidated. It also 1252934Sktlim@umich.edu * updates the replacement data. 1262995Ssaidi@eecs.umich.edu * 1272995Ssaidi@eecs.umich.edu * @param blk The block to invalidate. 1283025Ssaidi@eecs.umich.edu */ 1293025Ssaidi@eecs.umich.edu void invalidate(CacheBlk *blk) override; 1303025Ssaidi@eecs.umich.edu 1313025Ssaidi@eecs.umich.edu /** 1323025Ssaidi@eecs.umich.edu * Access block and update replacement data. May not succeed, in which case 1332934Sktlim@umich.edu * nullptr is returned. This has all the implications of a cache 1342934Sktlim@umich.edu * access and should only be used as such. Returns the access latency as a 135 * side effect. 136 * @param addr The address to find. 137 * @param is_secure True if the target memory space is secure. 138 * @param lat The access latency. 139 * @return Pointer to the cache block if found. 140 */ 141 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 142 { 143 BlkType *blk = findBlock(addr, is_secure); 144 145 // Access all tags in parallel, hence one in each way. The data side 146 // either accesses all blocks in parallel, or one block sequentially on 147 // a hit. Sequential access with a miss doesn't access data. 148 tagAccesses += allocAssoc; 149 if (sequentialAccess) { 150 if (blk != nullptr) { 151 dataAccesses += 1; 152 } 153 } else { 154 dataAccesses += allocAssoc; 155 } 156 157 if (blk != nullptr) { 158 // If a cache hit 159 lat = accessLatency; 160 // Check if the block to be accessed is available. If not, 161 // apply the accessLatency on top of block->whenReady. 162 if (blk->whenReady > curTick() && 163 cache->ticksToCycles(blk->whenReady - curTick()) > 164 accessLatency) { 165 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 166 accessLatency; 167 } 168 169 // Update number of references to accessed block 170 blk->refCount++; 171 172 // Update replacement data of accessed block 173 replacementPolicy->touch(blk->replacementData); 174 } else { 175 // If a cache miss 176 lat = lookupLatency; 177 } 178 179 return blk; 180 } 181 182 /** 183 * Finds the given address in the cache, do not update replacement data. 184 * i.e. This is a no-side-effect find of a block. 185 * 186 * @param addr The address to find. 187 * @param is_secure True if the target memory space is secure. 188 * @return Pointer to the cache block if found. 189 */ 190 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 191 192 /** 193 * Find a block given set and way. 194 * 195 * @param set The set of the block. 196 * @param way The way of the block. 197 * @return The block. 198 */ 199 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 200 201 /** 202 * Find replacement victim based on address. The list of evicted blocks 203 * only contains the victim. 204 * 205 * @param addr Address to find a victim for. 206 * @param is_secure True if the target memory space is secure. 207 * @param evict_blks Cache blocks to be evicted. 208 * @return Cache block to be replaced. 209 */ 210 CacheBlk* findVictim(Addr addr, const bool is_secure, 211 std::vector<CacheBlk*>& evict_blks) const override 212 { 213 // Get possible locations for the victim block 214 std::vector<CacheBlk*> locations = getPossibleLocations(addr); 215 216 // Choose replacement victim from replacement candidates 217 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim( 218 std::vector<ReplaceableEntry*>( 219 locations.begin(), locations.end()))); 220 221 // There is only one eviction for this replacement 222 evict_blks.push_back(victim); 223 224 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n", 225 victim->set, victim->way); 226 227 return victim; 228 } 229 230 /** 231 * Find all possible block locations for insertion and replacement of 232 * an address. Should be called immediately before ReplacementPolicy's 233 * findVictim() not to break cache resizing. 234 * Returns blocks in all ways belonging to the set of the address. 235 * 236 * @param addr The addr to a find possible locations for. 237 * @return The possible locations. 238 */ 239 virtual const std::vector<CacheBlk*> getPossibleLocations(Addr addr) const 240 { 241 return sets[extractSet(addr)].blks; 242 } 243 244 /** 245 * Insert the new block into the cache and update replacement data. 246 * 247 * @param addr Address of the block. 248 * @param is_secure Whether the block is in secure space or not. 249 * @param src_master_ID The source requestor ID. 250 * @param task_ID The new task ID. 251 * @param blk The block to update. 252 */ 253 void insertBlock(const Addr addr, const bool is_secure, 254 const int src_master_ID, const uint32_t task_ID, 255 CacheBlk *blk) override 256 { 257 // Insert block 258 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); 259 260 // Increment tag counter 261 tagsInUse++; 262 263 // Update replacement policy 264 replacementPolicy->reset(blk->replacementData); 265 } 266 267 /** 268 * Limit the allocation for the cache ways. 269 * @param ways The maximum number of ways available for replacement. 270 */ 271 virtual void setWayAllocationMax(int ways) override 272 { 273 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 274 allocAssoc = ways; 275 } 276 277 /** 278 * Get the way allocation mask limit. 279 * @return The maximum number of ways available for replacement. 280 */ 281 virtual int getWayAllocationMax() const override 282 { 283 return allocAssoc; 284 } 285 286 /** 287 * Generate the tag from the given address. 288 * @param addr The address to get the tag from. 289 * @return The tag of the address. 290 */ 291 Addr extractTag(Addr addr) const override 292 { 293 return (addr >> tagShift); 294 } 295 296 /** 297 * Regenerate the block address from the tag and set. 298 * 299 * @param block The block. 300 * @return the block address. 301 */ 302 Addr regenerateBlkAddr(const CacheBlk* blk) const override 303 { 304 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift)); 305 } 306 307 void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 308 for (CacheBlk& blk : blks) { 309 visitor(blk); 310 } 311 } 312 313 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 314 for (CacheBlk& blk : blks) { 315 if (visitor(blk)) { 316 return true; 317 } 318 } 319 return false; 320 } 321 322 private: 323 /** 324 * Calculate the set index from the address. 325 * 326 * @param addr The address to get the set from. 327 * @return The set index of the address. 328 */ 329 int extractSet(Addr addr) const 330 { 331 return ((addr >> setShift) & setMask); 332 } 333}; 334 335#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 336