base_set_assoc.hh revision 12574:22936e2eb2da
1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <cassert> 52#include <cstring> 53#include <memory> 54#include <vector> 55 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/tags/base.hh" 59#include "mem/cache/tags/cacheset.hh" 60#include "mem/packet.hh" 61#include "params/BaseSetAssoc.hh" 62 63/** 64 * A BaseSetAssoc cache tag store. 65 * @sa \ref gem5MemorySystem "gem5 Memory System" 66 * 67 * The BaseSetAssoc tags provide a base, as well as the functionality 68 * common to any set associative tags. Any derived class must implement 69 * the methods related to the specifics of the actual replacment policy. 70 * These are: 71 * 72 * BlkType* accessBlock(); 73 * BlkType* findVictim(); 74 * void insertBlock(); 75 */ 76class BaseSetAssoc : public BaseTags 77{ 78 public: 79 /** Typedef the block type used in this tag store. */ 80 typedef CacheBlk BlkType; 81 /** Typedef the set type used in this tag store. */ 82 typedef CacheSet<CacheBlk> SetType; 83 84 85 protected: 86 /** The associativity of the cache. */ 87 const unsigned assoc; 88 /** The allocatable associativity of the cache (alloc mask). */ 89 unsigned allocAssoc; 90 91 /** The cache blocks. */ 92 std::vector<BlkType> blks; 93 /** The data blocks, 1 per cache block. */ 94 std::unique_ptr<uint8_t[]> dataBlks; 95 96 /** The number of sets in the cache. */ 97 const unsigned numSets; 98 99 /** Whether tags and data are accessed sequentially. */ 100 const bool sequentialAccess; 101 102 /** The cache sets. */ 103 std::vector<SetType> sets; 104 105 /** The amount to shift the address to get the set. */ 106 int setShift; 107 /** The amount to shift the address to get the tag. */ 108 int tagShift; 109 /** Mask out all bits that aren't part of the set index. */ 110 unsigned setMask; 111 112public: 113 114 /** Convenience typedef. */ 115 typedef BaseSetAssocParams Params; 116 117 /** 118 * Construct and initialize this tag store. 119 */ 120 BaseSetAssoc(const Params *p); 121 122 /** 123 * Destructor 124 */ 125 virtual ~BaseSetAssoc() {}; 126 127 /** 128 * Find the cache block given set and way 129 * @param set The set of the block. 130 * @param way The way of the block. 131 * @return The cache block. 132 */ 133 CacheBlk *findBlockBySetAndWay(int set, int way) const override; 134 135 /** 136 * Access block and update replacement data. May not succeed, in which case 137 * nullptr is returned. This has all the implications of a cache 138 * access and should only be used as such. Returns the access latency as a 139 * side effect. 140 * @param addr The address to find. 141 * @param is_secure True if the target memory space is secure. 142 * @param lat The access latency. 143 * @return Pointer to the cache block if found. 144 */ 145 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 146 { 147 BlkType *blk = findBlock(addr, is_secure); 148 149 // Access all tags in parallel, hence one in each way. The data side 150 // either accesses all blocks in parallel, or one block sequentially on 151 // a hit. Sequential access with a miss doesn't access data. 152 tagAccesses += allocAssoc; 153 if (sequentialAccess) { 154 if (blk != nullptr) { 155 dataAccesses += 1; 156 } 157 } else { 158 dataAccesses += allocAssoc; 159 } 160 161 if (blk != nullptr) { 162 // If a cache hit 163 lat = accessLatency; 164 // Check if the block to be accessed is available. If not, 165 // apply the accessLatency on top of block->whenReady. 166 if (blk->whenReady > curTick() && 167 cache->ticksToCycles(blk->whenReady - curTick()) > 168 accessLatency) { 169 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 170 accessLatency; 171 } 172 blk->refCount += 1; 173 } else { 174 // If a cache miss 175 lat = lookupLatency; 176 } 177 178 return blk; 179 } 180 181 /** 182 * Finds the given address in the cache, do not update replacement data. 183 * i.e. This is a no-side-effect find of a block. 184 * @param addr The address to find. 185 * @param is_secure True if the target memory space is secure. 186 * @param asid The address space ID. 187 * @return Pointer to the cache block if found. 188 */ 189 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 190 191 /** 192 * Find an invalid block to evict for the address provided. 193 * If there are no invalid blocks, this will return the block 194 * in the least-recently-used position. 195 * @param addr The addr to a find a replacement candidate for. 196 * @return The candidate block. 197 */ 198 CacheBlk* findVictim(Addr addr) override 199 { 200 BlkType *blk = nullptr; 201 int set = extractSet(addr); 202 203 // prefer to evict an invalid block 204 for (int i = 0; i < allocAssoc; ++i) { 205 blk = sets[set].blks[i]; 206 if (!blk->isValid()) 207 break; 208 } 209 210 return blk; 211 } 212 213 /** 214 * Insert the new block into the cache. 215 * @param pkt Packet holding the address to update 216 * @param blk The block to update. 217 */ 218 void insertBlock(PacketPtr pkt, CacheBlk *blk) override 219 { 220 Addr addr = pkt->getAddr(); 221 MasterID master_id = pkt->req->masterId(); 222 uint32_t task_id = pkt->req->taskId(); 223 224 if (!blk->isTouched) { 225 if (!warmedUp && tagsInUse.value() >= warmupBound) { 226 warmedUp = true; 227 warmupCycle = curTick(); 228 } 229 } 230 231 // If we're replacing a block that was previously valid update 232 // stats for it. This can't be done in findBlock() because a 233 // found block might not actually be replaced there if the 234 // coherence protocol says it can't be. 235 if (blk->isValid()) { 236 replacements[0]++; 237 totalRefs += blk->refCount; 238 ++sampledRefs; 239 240 invalidate(blk); 241 blk->invalidate(); 242 } 243 244 // Previous block, if existed, has been removed, and now we have 245 // to insert the new one and mark it as touched 246 tagsInUse++; 247 blk->isTouched = true; 248 249 // Set tag for new block. Caller is responsible for setting status. 250 blk->tag = extractTag(addr); 251 252 // deal with what we are bringing in 253 assert(master_id < cache->system->maxMasters()); 254 occupancies[master_id]++; 255 blk->srcMasterId = master_id; 256 blk->task_id = task_id; 257 blk->tickInserted = curTick(); 258 259 // We only need to write into one tag and one data block. 260 tagAccesses += 1; 261 dataAccesses += 1; 262 } 263 264 /** 265 * Limit the allocation for the cache ways. 266 * @param ways The maximum number of ways available for replacement. 267 */ 268 virtual void setWayAllocationMax(int ways) override 269 { 270 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 271 allocAssoc = ways; 272 } 273 274 /** 275 * Get the way allocation mask limit. 276 * @return The maximum number of ways available for replacement. 277 */ 278 virtual int getWayAllocationMax() const override 279 { 280 return allocAssoc; 281 } 282 283 /** 284 * Generate the tag from the given address. 285 * @param addr The address to get the tag from. 286 * @return The tag of the address. 287 */ 288 Addr extractTag(Addr addr) const override 289 { 290 return (addr >> tagShift); 291 } 292 293 /** 294 * Calculate the set index from the address. 295 * @param addr The address to get the set from. 296 * @return The set index of the address. 297 */ 298 int extractSet(Addr addr) const override 299 { 300 return ((addr >> setShift) & setMask); 301 } 302 303 /** 304 * Regenerate the block address from the tag and set. 305 * 306 * @param block The block. 307 * @return the block address. 308 */ 309 Addr regenerateBlkAddr(const CacheBlk* blk) const override 310 { 311 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift)); 312 } 313 314 /** 315 * Called at end of simulation to complete average block reference stats. 316 */ 317 void cleanupRefs() override; 318 319 /** 320 * Print all tags used 321 */ 322 std::string print() const override; 323 324 /** 325 * Called prior to dumping stats to compute task occupancy 326 */ 327 void computeStats() override; 328 329 /** 330 * Visit each block in the tag store and apply a visitor to the 331 * block. 332 * 333 * The visitor should be a function (or object that behaves like a 334 * function) that takes a cache block reference as its parameter 335 * and returns a bool. A visitor can request the traversal to be 336 * stopped by returning false, returning true causes it to be 337 * called for the next block in the tag store. 338 * 339 * \param visitor Visitor to call on each block. 340 */ 341 void forEachBlk(CacheBlkVisitor &visitor) override { 342 for (unsigned i = 0; i < numSets * assoc; ++i) { 343 if (!visitor(blks[i])) 344 return; 345 } 346 } 347}; 348 349#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 350