base_set_assoc.hh revision 11870:b470020b29de
1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASESETASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASESETASSOC_HH__ 50 51#include <cassert> 52#include <cstring> 53#include <list> 54 55#include "mem/cache/base.hh" 56#include "mem/cache/blk.hh" 57#include "mem/cache/tags/base.hh" 58#include "mem/cache/tags/cacheset.hh" 59#include "mem/packet.hh" 60#include "params/BaseSetAssoc.hh" 61 62/** 63 * A BaseSetAssoc cache tag store. 64 * @sa \ref gem5MemorySystem "gem5 Memory System" 65 * 66 * The BaseSetAssoc tags provide a base, as well as the functionality 67 * common to any set associative tags. Any derived class must implement 68 * the methods related to the specifics of the actual replacment policy. 69 * These are: 70 * 71 * BlkType* accessBlock(); 72 * BlkType* findVictim(); 73 * void insertBlock(); 74 * void invalidate(); 75 */ 76class BaseSetAssoc : public BaseTags 77{ 78 public: 79 /** Typedef the block type used in this tag store. */ 80 typedef CacheBlk BlkType; 81 /** Typedef the set type used in this tag store. */ 82 typedef CacheSet<CacheBlk> SetType; 83 84 85 protected: 86 /** The associativity of the cache. */ 87 const unsigned assoc; 88 /** The allocatable associativity of the cache (alloc mask). */ 89 unsigned allocAssoc; 90 /** The number of sets in the cache. */ 91 const unsigned numSets; 92 /** Whether tags and data are accessed sequentially. */ 93 const bool sequentialAccess; 94 95 /** The cache sets. */ 96 SetType *sets; 97 98 /** The cache blocks. */ 99 BlkType *blks; 100 /** The data blocks, 1 per cache block. */ 101 uint8_t *dataBlks; 102 103 /** The amount to shift the address to get the set. */ 104 int setShift; 105 /** The amount to shift the address to get the tag. */ 106 int tagShift; 107 /** Mask out all bits that aren't part of the set index. */ 108 unsigned setMask; 109 /** Mask out all bits that aren't part of the block offset. */ 110 unsigned blkMask; 111 112public: 113 114 /** Convenience typedef. */ 115 typedef BaseSetAssocParams Params; 116 117 /** 118 * Construct and initialize this tag store. 119 */ 120 BaseSetAssoc(const Params *p); 121 122 /** 123 * Destructor 124 */ 125 virtual ~BaseSetAssoc(); 126 127 /** 128 * Find the cache block given set and way 129 * @param set The set of the block. 130 * @param way The way of the block. 131 * @return The cache block. 132 */ 133 CacheBlk *findBlockBySetAndWay(int set, int way) const override; 134 135 /** 136 * Invalidate the given block. 137 * @param blk The block to invalidate. 138 */ 139 void invalidate(CacheBlk *blk) override 140 { 141 assert(blk); 142 assert(blk->isValid()); 143 tagsInUse--; 144 assert(blk->srcMasterId < cache->system->maxMasters()); 145 occupancies[blk->srcMasterId]--; 146 blk->srcMasterId = Request::invldMasterId; 147 blk->task_id = ContextSwitchTaskId::Unknown; 148 blk->tickInserted = curTick(); 149 } 150 151 /** 152 * Access block and update replacement data. May not succeed, in which case 153 * nullptr is returned. This has all the implications of a cache 154 * access and should only be used as such. Returns the access latency as a 155 * side effect. 156 * @param addr The address to find. 157 * @param is_secure True if the target memory space is secure. 158 * @param lat The access latency. 159 * @return Pointer to the cache block if found. 160 */ 161 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 162 { 163 Addr tag = extractTag(addr); 164 int set = extractSet(addr); 165 BlkType *blk = sets[set].findBlk(tag, is_secure); 166 167 // Access all tags in parallel, hence one in each way. The data side 168 // either accesses all blocks in parallel, or one block sequentially on 169 // a hit. Sequential access with a miss doesn't access data. 170 tagAccesses += allocAssoc; 171 if (sequentialAccess) { 172 if (blk != nullptr) { 173 dataAccesses += 1; 174 } 175 } else { 176 dataAccesses += allocAssoc; 177 } 178 179 if (blk != nullptr) { 180 // If a cache hit 181 lat = accessLatency; 182 // Check if the block to be accessed is available. If not, 183 // apply the accessLatency on top of block->whenReady. 184 if (blk->whenReady > curTick() && 185 cache->ticksToCycles(blk->whenReady - curTick()) > 186 accessLatency) { 187 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 188 accessLatency; 189 } 190 blk->refCount += 1; 191 } else { 192 // If a cache miss 193 lat = lookupLatency; 194 } 195 196 return blk; 197 } 198 199 /** 200 * Finds the given address in the cache, do not update replacement data. 201 * i.e. This is a no-side-effect find of a block. 202 * @param addr The address to find. 203 * @param is_secure True if the target memory space is secure. 204 * @param asid The address space ID. 205 * @return Pointer to the cache block if found. 206 */ 207 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 208 209 /** 210 * Find an invalid block to evict for the address provided. 211 * If there are no invalid blocks, this will return the block 212 * in the least-recently-used position. 213 * @param addr The addr to a find a replacement candidate for. 214 * @return The candidate block. 215 */ 216 CacheBlk* findVictim(Addr addr) override 217 { 218 BlkType *blk = nullptr; 219 int set = extractSet(addr); 220 221 // prefer to evict an invalid block 222 for (int i = 0; i < allocAssoc; ++i) { 223 blk = sets[set].blks[i]; 224 if (!blk->isValid()) 225 break; 226 } 227 228 return blk; 229 } 230 231 /** 232 * Insert the new block into the cache. 233 * @param pkt Packet holding the address to update 234 * @param blk The block to update. 235 */ 236 void insertBlock(PacketPtr pkt, CacheBlk *blk) override 237 { 238 Addr addr = pkt->getAddr(); 239 MasterID master_id = pkt->req->masterId(); 240 uint32_t task_id = pkt->req->taskId(); 241 242 if (!blk->isTouched) { 243 tagsInUse++; 244 blk->isTouched = true; 245 if (!warmedUp && tagsInUse.value() >= warmupBound) { 246 warmedUp = true; 247 warmupCycle = curTick(); 248 } 249 } 250 251 // If we're replacing a block that was previously valid update 252 // stats for it. This can't be done in findBlock() because a 253 // found block might not actually be replaced there if the 254 // coherence protocol says it can't be. 255 if (blk->isValid()) { 256 replacements[0]++; 257 totalRefs += blk->refCount; 258 ++sampledRefs; 259 blk->refCount = 0; 260 261 // deal with evicted block 262 assert(blk->srcMasterId < cache->system->maxMasters()); 263 occupancies[blk->srcMasterId]--; 264 265 blk->invalidate(); 266 } 267 268 blk->isTouched = true; 269 270 // Set tag for new block. Caller is responsible for setting status. 271 blk->tag = extractTag(addr); 272 273 // deal with what we are bringing in 274 assert(master_id < cache->system->maxMasters()); 275 occupancies[master_id]++; 276 blk->srcMasterId = master_id; 277 blk->task_id = task_id; 278 blk->tickInserted = curTick(); 279 280 // We only need to write into one tag and one data block. 281 tagAccesses += 1; 282 dataAccesses += 1; 283 } 284 285 /** 286 * Limit the allocation for the cache ways. 287 * @param ways The maximum number of ways available for replacement. 288 */ 289 virtual void setWayAllocationMax(int ways) override 290 { 291 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 292 allocAssoc = ways; 293 } 294 295 /** 296 * Get the way allocation mask limit. 297 * @return The maximum number of ways available for replacement. 298 */ 299 virtual int getWayAllocationMax() const override 300 { 301 return allocAssoc; 302 } 303 304 /** 305 * Generate the tag from the given address. 306 * @param addr The address to get the tag from. 307 * @return The tag of the address. 308 */ 309 Addr extractTag(Addr addr) const override 310 { 311 return (addr >> tagShift); 312 } 313 314 /** 315 * Calculate the set index from the address. 316 * @param addr The address to get the set from. 317 * @return The set index of the address. 318 */ 319 int extractSet(Addr addr) const override 320 { 321 return ((addr >> setShift) & setMask); 322 } 323 324 /** 325 * Align an address to the block size. 326 * @param addr the address to align. 327 * @return The block address. 328 */ 329 Addr blkAlign(Addr addr) const 330 { 331 return (addr & ~(Addr)blkMask); 332 } 333 334 /** 335 * Regenerate the block address from the tag. 336 * @param tag The tag of the block. 337 * @param set The set of the block. 338 * @return The block address. 339 */ 340 Addr regenerateBlkAddr(Addr tag, unsigned set) const override 341 { 342 return ((tag << tagShift) | ((Addr)set << setShift)); 343 } 344 345 /** 346 * Called at end of simulation to complete average block reference stats. 347 */ 348 void cleanupRefs() override; 349 350 /** 351 * Print all tags used 352 */ 353 std::string print() const override; 354 355 /** 356 * Called prior to dumping stats to compute task occupancy 357 */ 358 void computeStats() override; 359 360 /** 361 * Visit each block in the tag store and apply a visitor to the 362 * block. 363 * 364 * The visitor should be a function (or object that behaves like a 365 * function) that takes a cache block reference as its parameter 366 * and returns a bool. A visitor can request the traversal to be 367 * stopped by returning false, returning true causes it to be 368 * called for the next block in the tag store. 369 * 370 * \param visitor Visitor to call on each block. 371 */ 372 void forEachBlk(CacheBlkVisitor &visitor) override { 373 for (unsigned i = 0; i < numSets * assoc; ++i) { 374 if (!visitor(blks[i])) 375 return; 376 } 377 } 378}; 379 380#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__ 381