base_set_assoc.hh revision 13216
1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <functional> 52#include <string> 53#include <vector> 54 55#include "base/logging.hh" 56#include "base/types.hh" 57#include "debug/CacheRepl.hh" 58#include "mem/cache/base.hh" 59#include "mem/cache/blk.hh" 60#include "mem/cache/replacement_policies/base.hh" 61#include "mem/cache/tags/base.hh" 62#include "mem/cache/tags/cacheset.hh" 63#include "params/BaseSetAssoc.hh" 64 65/** 66 * A BaseSetAssoc cache tag store. 67 * @sa \ref gem5MemorySystem "gem5 Memory System" 68 * 69 * The BaseSetAssoc placement policy divides the cache into s sets of w 70 * cache lines (ways). A cache line is mapped onto a set, and can be placed 71 * into any of the ways of this set. 72 */ 73class BaseSetAssoc : public BaseTags 74{ 75 public: 76 /** Typedef the block type used in this tag store. */ 77 typedef CacheBlk BlkType; 78 /** Typedef the set type used in this tag store. */ 79 typedef CacheSet<CacheBlk> SetType; 80 81 protected: 82 /** The associativity of the cache. */ 83 const unsigned assoc; 84 /** The allocatable associativity of the cache (alloc mask). */ 85 unsigned allocAssoc; 86 87 /** The cache blocks. */ 88 std::vector<BlkType> blks; 89 90 /** The number of sets in the cache. */ 91 const unsigned numSets; 92 93 /** Whether tags and data are accessed sequentially. */ 94 const bool sequentialAccess; 95 96 /** The cache sets. */ 97 std::vector<SetType> sets; 98 99 /** The amount to shift the address to get the set. */ 100 int setShift; 101 /** The amount to shift the address to get the tag. */ 102 int tagShift; 103 /** Mask out all bits that aren't part of the set index. */ 104 unsigned setMask; 105 106 /** Replacement policy */ 107 BaseReplacementPolicy *replacementPolicy; 108 109 public: 110 /** Convenience typedef. */ 111 typedef BaseSetAssocParams Params; 112 113 /** 114 * Construct and initialize this tag store. 115 */ 116 BaseSetAssoc(const Params *p); 117 118 /** 119 * Destructor 120 */ 121 virtual ~BaseSetAssoc() {}; 122 123 /** 124 * Initialize blocks and set the parent cache back pointer. 125 * 126 * @param _cache Pointer to parent cache. 127 */ 128 void init(BaseCache *_cache) override; 129 130 /** 131 * This function updates the tags when a block is invalidated. It also 132 * updates the replacement data. 133 * 134 * @param blk The block to invalidate. 135 */ 136 void invalidate(CacheBlk *blk) override; 137 138 /** 139 * Access block and update replacement data. May not succeed, in which case 140 * nullptr is returned. This has all the implications of a cache 141 * access and should only be used as such. Returns the access latency as a 142 * side effect. 143 * @param addr The address to find. 144 * @param is_secure True if the target memory space is secure. 145 * @param lat The access latency. 146 * @return Pointer to the cache block if found. 147 */ 148 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 149 { 150 BlkType *blk = findBlock(addr, is_secure); 151 152 // Access all tags in parallel, hence one in each way. The data side 153 // either accesses all blocks in parallel, or one block sequentially on 154 // a hit. Sequential access with a miss doesn't access data. 155 tagAccesses += allocAssoc; 156 if (sequentialAccess) { 157 if (blk != nullptr) { 158 dataAccesses += 1; 159 } 160 } else { 161 dataAccesses += allocAssoc; 162 } 163 164 if (blk != nullptr) { 165 // If a cache hit 166 lat = accessLatency; 167 // Check if the block to be accessed is available. If not, 168 // apply the accessLatency on top of block->whenReady. 169 if (blk->whenReady > curTick() && 170 cache->ticksToCycles(blk->whenReady - curTick()) > 171 accessLatency) { 172 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 173 accessLatency; 174 } 175 176 // Update number of references to accessed block 177 blk->refCount++; 178 179 // Update replacement data of accessed block 180 replacementPolicy->touch(blk->replacementData); 181 } else { 182 // If a cache miss 183 lat = lookupLatency; 184 } 185 186 return blk; 187 } 188 189 /** 190 * Finds the given address in the cache, do not update replacement data. 191 * i.e. This is a no-side-effect find of a block. 192 * 193 * @param addr The address to find. 194 * @param is_secure True if the target memory space is secure. 195 * @return Pointer to the cache block if found. 196 */ 197 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 198 199 /** 200 * Find a block given set and way. 201 * 202 * @param set The set of the block. 203 * @param way The way of the block. 204 * @return The block. 205 */ 206 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 207 208 /** 209 * Find replacement victim based on address. The list of evicted blocks 210 * only contains the victim. 211 * 212 * @param addr Address to find a victim for. 213 * @param is_secure True if the target memory space is secure. 214 * @param evict_blks Cache blocks to be evicted. 215 * @return Cache block to be replaced. 216 */ 217 CacheBlk* findVictim(Addr addr, const bool is_secure, 218 std::vector<CacheBlk*>& evict_blks) const override 219 { 220 // Get possible locations for the victim block 221 std::vector<CacheBlk*> locations = getPossibleLocations(addr); 222 223 // Choose replacement victim from replacement candidates 224 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim( 225 std::vector<ReplaceableEntry*>( 226 locations.begin(), locations.end()))); 227 228 // There is only one eviction for this replacement 229 evict_blks.push_back(victim); 230 231 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n", 232 victim->set, victim->way); 233 234 return victim; 235 } 236 237 /** 238 * Find all possible block locations for insertion and replacement of 239 * an address. Should be called immediately before ReplacementPolicy's 240 * findVictim() not to break cache resizing. 241 * Returns blocks in all ways belonging to the set of the address. 242 * 243 * @param addr The addr to a find possible locations for. 244 * @return The possible locations. 245 */ 246 virtual const std::vector<CacheBlk*> getPossibleLocations(Addr addr) const 247 { 248 return sets[extractSet(addr)].blks; 249 } 250 251 /** 252 * Insert the new block into the cache and update replacement data. 253 * 254 * @param addr Address of the block. 255 * @param is_secure Whether the block is in secure space or not. 256 * @param src_master_ID The source requestor ID. 257 * @param task_ID The new task ID. 258 * @param blk The block to update. 259 */ 260 void insertBlock(const Addr addr, const bool is_secure, 261 const int src_master_ID, const uint32_t task_ID, 262 CacheBlk *blk) override 263 { 264 // Insert block 265 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); 266 267 // Increment tag counter 268 tagsInUse++; 269 270 // Update replacement policy 271 replacementPolicy->reset(blk->replacementData); 272 } 273 274 /** 275 * Limit the allocation for the cache ways. 276 * @param ways The maximum number of ways available for replacement. 277 */ 278 virtual void setWayAllocationMax(int ways) override 279 { 280 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 281 allocAssoc = ways; 282 } 283 284 /** 285 * Get the way allocation mask limit. 286 * @return The maximum number of ways available for replacement. 287 */ 288 virtual int getWayAllocationMax() const override 289 { 290 return allocAssoc; 291 } 292 293 /** 294 * Generate the tag from the given address. 295 * @param addr The address to get the tag from. 296 * @return The tag of the address. 297 */ 298 Addr extractTag(Addr addr) const override 299 { 300 return (addr >> tagShift); 301 } 302 303 /** 304 * Regenerate the block address from the tag and set. 305 * 306 * @param block The block. 307 * @return the block address. 308 */ 309 Addr regenerateBlkAddr(const CacheBlk* blk) const override 310 { 311 return ((blk->tag << tagShift) | ((Addr)blk->set << setShift)); 312 } 313 314 void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 315 for (CacheBlk& blk : blks) { 316 visitor(blk); 317 } 318 } 319 320 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 321 for (CacheBlk& blk : blks) { 322 if (visitor(blk)) { 323 return true; 324 } 325 } 326 return false; 327 } 328 329 private: 330 /** 331 * Calculate the set index from the address. 332 * 333 * @param addr The address to get the set from. 334 * @return The set index of the address. 335 */ 336 int extractSet(Addr addr) const 337 { 338 return ((addr >> setShift) & setMask); 339 } 340}; 341 342#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 343