base.hh revision 11722:f15f02d8c79e
1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Ron Dreslinski 42 */ 43 44/** 45 * @file 46 * Declaration of a common base class for cache tagstore objects. 47 */ 48 49#ifndef __BASE_TAGS_HH__ 50#define __BASE_TAGS_HH__ 51 52#include <string> 53 54#include "base/callback.hh" 55#include "base/statistics.hh" 56#include "mem/cache/blk.hh" 57#include "params/BaseTags.hh" 58#include "sim/clocked_object.hh" 59 60class BaseCache; 61 62/** 63 * A common base class of Cache tagstore objects. 64 */ 65class BaseTags : public ClockedObject 66{ 67 protected: 68 /** The block size of the cache. */ 69 const unsigned blkSize; 70 /** The size of the cache. */ 71 const unsigned size; 72 /** The tag lookup latency of the cache. */ 73 const Cycles lookupLatency; 74 /** 75 * The total access latency of the cache. This latency 76 * is different depending on the cache access mode 77 * (parallel or sequential) 78 */ 79 const Cycles accessLatency; 80 /** Pointer to the parent cache. */ 81 BaseCache *cache; 82 83 /** 84 * The number of tags that need to be touched to meet the warmup 85 * percentage. 86 */ 87 int warmupBound; 88 /** Marked true when the cache is warmed up. */ 89 bool warmedUp; 90 91 /** the number of blocks in the cache */ 92 unsigned numBlocks; 93 94 // Statistics 95 /** 96 * @addtogroup CacheStatistics 97 * @{ 98 */ 99 100 /** Number of replacements of valid blocks per thread. */ 101 Stats::Vector replacements; 102 /** Per cycle average of the number of tags that hold valid data. */ 103 Stats::Average tagsInUse; 104 105 /** The total number of references to a block before it is replaced. */ 106 Stats::Scalar totalRefs; 107 108 /** 109 * The number of reference counts sampled. This is different from 110 * replacements because we sample all the valid blocks when the simulator 111 * exits. 112 */ 113 Stats::Scalar sampledRefs; 114 115 /** 116 * Average number of references to a block before is was replaced. 117 * @todo This should change to an average stat once we have them. 118 */ 119 Stats::Formula avgRefs; 120 121 /** The cycle that the warmup percentage was hit. */ 122 Stats::Scalar warmupCycle; 123 124 /** Average occupancy of each requestor using the cache */ 125 Stats::AverageVector occupancies; 126 127 /** Average occ % of each requestor using the cache */ 128 Stats::Formula avgOccs; 129 130 /** Occupancy of each context/cpu using the cache */ 131 Stats::Vector occupanciesTaskId; 132 133 /** Occupancy of each context/cpu using the cache */ 134 Stats::Vector2d ageTaskId; 135 136 /** Occ % of each context/cpu using the cache */ 137 Stats::Formula percentOccsTaskId; 138 139 /** Number of tags consulted over all accesses. */ 140 Stats::Scalar tagAccesses; 141 /** Number of data blocks consulted over all accesses. */ 142 Stats::Scalar dataAccesses; 143 144 /** 145 * @} 146 */ 147 148 public: 149 typedef BaseTagsParams Params; 150 BaseTags(const Params *p); 151 152 /** 153 * Destructor. 154 */ 155 virtual ~BaseTags() {} 156 157 /** 158 * Set the parent cache back pointer. 159 * @param _cache Pointer to parent cache. 160 */ 161 void setCache(BaseCache *_cache); 162 163 /** 164 * Register local statistics. 165 */ 166 void regStats(); 167 168 /** 169 * Average in the reference count for valid blocks when the simulation 170 * exits. 171 */ 172 virtual void cleanupRefs() {} 173 174 /** 175 * Computes stats just prior to dump event 176 */ 177 virtual void computeStats() {} 178 179 /** 180 * Print all tags used 181 */ 182 virtual std::string print() const = 0; 183 184 /** 185 * Find a block using the memory address 186 */ 187 virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0; 188 189 /** 190 * Calculate the block offset of an address. 191 * @param addr the address to get the offset of. 192 * @return the block offset. 193 */ 194 int extractBlkOffset(Addr addr) const 195 { 196 return (addr & (Addr)(blkSize-1)); 197 } 198 199 /** 200 * Find the cache block given set and way 201 * @param set The set of the block. 202 * @param way The way of the block. 203 * @return The cache block. 204 */ 205 virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0; 206 207 /** 208 * Limit the allocation for the cache ways. 209 * @param ways The maximum number of ways available for replacement. 210 */ 211 virtual void setWayAllocationMax(int ways) 212 { 213 panic("This tag class does not implement way allocation limit!\n"); 214 } 215 216 /** 217 * Get the way allocation mask limit. 218 * @return The maximum number of ways available for replacement. 219 */ 220 virtual int getWayAllocationMax() const 221 { 222 panic("This tag class does not implement way allocation limit!\n"); 223 return -1; 224 } 225 226 virtual unsigned getNumSets() const = 0; 227 228 virtual unsigned getNumWays() const = 0; 229 230 virtual void invalidate(CacheBlk *blk) = 0; 231 232 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 233 int context_src) = 0; 234 235 virtual Addr extractTag(Addr addr) const = 0; 236 237 virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0; 238 239 virtual Addr regenerateBlkAddr(Addr tag, unsigned set) const = 0; 240 241 virtual CacheBlk* findVictim(Addr addr) = 0; 242 243 virtual int extractSet(Addr addr) const = 0; 244 245 virtual void forEachBlk(CacheBlkVisitor &visitor) = 0; 246}; 247 248class BaseTagsCallback : public Callback 249{ 250 BaseTags *tags; 251 public: 252 BaseTagsCallback(BaseTags *t) : tags(t) {} 253 virtual void process() { tags->cleanupRefs(); }; 254}; 255 256class BaseTagsDumpCallback : public Callback 257{ 258 BaseTags *tags; 259 public: 260 BaseTagsDumpCallback(BaseTags *t) : tags(t) {} 261 virtual void process() { tags->computeStats(); }; 262}; 263 264#endif //__BASE_TAGS_HH__ 265