base.hh revision 12636
12810SN/A/* 212566Snikos.nikoleris@arm.com * Copyright (c) 2012-2014,2016-2017 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A * Ron Dreslinski 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Declaration of a common base class for cache tagstore objects. 472810SN/A */ 482810SN/A 4912492Sodanrc@yahoo.com.br#ifndef __MEM_CACHE_TAGS_BASE_HH__ 5012492Sodanrc@yahoo.com.br#define __MEM_CACHE_TAGS_BASE_HH__ 512810SN/A 522810SN/A#include <string> 538229Snate@binkert.org 548229Snate@binkert.org#include "base/callback.hh" 552810SN/A#include "base/statistics.hh" 5610815Sdavid.guillen@arm.com#include "mem/cache/blk.hh" 5712600Sodanrc@yahoo.com.br#include "mem/cache/replacement_policies/base.hh" 589796Sprakash.ramrakhyani@arm.com#include "params/BaseTags.hh" 599796Sprakash.ramrakhyani@arm.com#include "sim/clocked_object.hh" 602810SN/A 612810SN/Aclass BaseCache; 622810SN/A 632810SN/A/** 642810SN/A * A common base class of Cache tagstore objects. 652810SN/A */ 669796Sprakash.ramrakhyani@arm.comclass BaseTags : public ClockedObject 672810SN/A{ 682810SN/A protected: 699796Sprakash.ramrakhyani@arm.com /** The block size of the cache. */ 709796Sprakash.ramrakhyani@arm.com const unsigned blkSize; 7111893Snikos.nikoleris@arm.com /** Mask out all bits that aren't part of the block offset. */ 7211893Snikos.nikoleris@arm.com const Addr blkMask; 739796Sprakash.ramrakhyani@arm.com /** The size of the cache. */ 749796Sprakash.ramrakhyani@arm.com const unsigned size; 7511722Ssophiane.senni@gmail.com /** The tag lookup latency of the cache. */ 7611722Ssophiane.senni@gmail.com const Cycles lookupLatency; 7711722Ssophiane.senni@gmail.com /** 7811722Ssophiane.senni@gmail.com * The total access latency of the cache. This latency 7911722Ssophiane.senni@gmail.com * is different depending on the cache access mode 8011722Ssophiane.senni@gmail.com * (parallel or sequential) 8111722Ssophiane.senni@gmail.com */ 8210693SMarco.Balboni@ARM.com const Cycles accessLatency; 832810SN/A /** Pointer to the parent cache. */ 842810SN/A BaseCache *cache; 852810SN/A 862810SN/A /** 872810SN/A * The number of tags that need to be touched to meet the warmup 882810SN/A * percentage. 892810SN/A */ 9012513Sodanrc@yahoo.com.br const unsigned warmupBound; 912810SN/A /** Marked true when the cache is warmed up. */ 922810SN/A bool warmedUp; 932810SN/A 946978SLisa.Hsu@amd.com /** the number of blocks in the cache */ 9512553Snikos.nikoleris@arm.com const unsigned numBlocks; 966978SLisa.Hsu@amd.com 9712629Sodanrc@yahoo.com.br /** The data blocks, 1 per cache block. */ 9812629Sodanrc@yahoo.com.br std::unique_ptr<uint8_t[]> dataBlks; 9912629Sodanrc@yahoo.com.br 1002810SN/A // Statistics 1012810SN/A /** 10212513Sodanrc@yahoo.com.br * TODO: It would be good if these stats were acquired after warmup. 1032810SN/A * @addtogroup CacheStatistics 1042810SN/A * @{ 1052810SN/A */ 1062810SN/A 1072810SN/A /** Number of replacements of valid blocks per thread. */ 1085999Snate@binkert.org Stats::Vector replacements; 1092810SN/A /** Per cycle average of the number of tags that hold valid data. */ 1105999Snate@binkert.org Stats::Average tagsInUse; 1112810SN/A 1122810SN/A /** The total number of references to a block before it is replaced. */ 1135999Snate@binkert.org Stats::Scalar totalRefs; 1142810SN/A 1152810SN/A /** 1162810SN/A * The number of reference counts sampled. This is different from 1172810SN/A * replacements because we sample all the valid blocks when the simulator 1182810SN/A * exits. 1192810SN/A */ 1205999Snate@binkert.org Stats::Scalar sampledRefs; 1212810SN/A 1222810SN/A /** 1232810SN/A * Average number of references to a block before is was replaced. 1242810SN/A * @todo This should change to an average stat once we have them. 1252810SN/A */ 1262810SN/A Stats::Formula avgRefs; 1272810SN/A 12812513Sodanrc@yahoo.com.br /** The cycle that the warmup percentage was hit. 0 on failure. */ 1295999Snate@binkert.org Stats::Scalar warmupCycle; 1306978SLisa.Hsu@amd.com 1318833Sdam.sunwoo@arm.com /** Average occupancy of each requestor using the cache */ 1326978SLisa.Hsu@amd.com Stats::AverageVector occupancies; 1336978SLisa.Hsu@amd.com 1348833Sdam.sunwoo@arm.com /** Average occ % of each requestor using the cache */ 1356978SLisa.Hsu@amd.com Stats::Formula avgOccs; 1366978SLisa.Hsu@amd.com 13710024Sdam.sunwoo@arm.com /** Occupancy of each context/cpu using the cache */ 13810024Sdam.sunwoo@arm.com Stats::Vector occupanciesTaskId; 13910024Sdam.sunwoo@arm.com 14010024Sdam.sunwoo@arm.com /** Occupancy of each context/cpu using the cache */ 14110024Sdam.sunwoo@arm.com Stats::Vector2d ageTaskId; 14210024Sdam.sunwoo@arm.com 14310024Sdam.sunwoo@arm.com /** Occ % of each context/cpu using the cache */ 14410024Sdam.sunwoo@arm.com Stats::Formula percentOccsTaskId; 14510024Sdam.sunwoo@arm.com 14610025Stimothy.jones@arm.com /** Number of tags consulted over all accesses. */ 14710025Stimothy.jones@arm.com Stats::Scalar tagAccesses; 14810025Stimothy.jones@arm.com /** Number of data blocks consulted over all accesses. */ 14910025Stimothy.jones@arm.com Stats::Scalar dataAccesses; 15010025Stimothy.jones@arm.com 1512810SN/A /** 1522810SN/A * @} 1532810SN/A */ 1542810SN/A 1552810SN/A public: 1569796Sprakash.ramrakhyani@arm.com typedef BaseTagsParams Params; 1579796Sprakash.ramrakhyani@arm.com BaseTags(const Params *p); 1582810SN/A 1592810SN/A /** 1602810SN/A * Destructor. 1612810SN/A */ 1622810SN/A virtual ~BaseTags() {} 1632810SN/A 1642810SN/A /** 1659796Sprakash.ramrakhyani@arm.com * Set the parent cache back pointer. 1662810SN/A * @param _cache Pointer to parent cache. 1672810SN/A */ 1682810SN/A void setCache(BaseCache *_cache); 1692810SN/A 1702810SN/A /** 1719796Sprakash.ramrakhyani@arm.com * Register local statistics. 1722810SN/A */ 1739796Sprakash.ramrakhyani@arm.com void regStats(); 1742810SN/A 1752810SN/A /** 1762810SN/A * Average in the reference count for valid blocks when the simulation 1772810SN/A * exits. 1782810SN/A */ 1792810SN/A virtual void cleanupRefs() {} 1807612SGene.Wu@arm.com 1817612SGene.Wu@arm.com /** 18210024Sdam.sunwoo@arm.com * Computes stats just prior to dump event 18310024Sdam.sunwoo@arm.com */ 18410024Sdam.sunwoo@arm.com virtual void computeStats() {} 18510024Sdam.sunwoo@arm.com 18610024Sdam.sunwoo@arm.com /** 1879663Suri.wiener@arm.com * Print all tags used 1889663Suri.wiener@arm.com */ 1899663Suri.wiener@arm.com virtual std::string print() const = 0; 19010815Sdavid.guillen@arm.com 19110815Sdavid.guillen@arm.com /** 19210815Sdavid.guillen@arm.com * Find a block using the memory address 19310815Sdavid.guillen@arm.com */ 19410815Sdavid.guillen@arm.com virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0; 19510815Sdavid.guillen@arm.com 19610815Sdavid.guillen@arm.com /** 19711893Snikos.nikoleris@arm.com * Align an address to the block size. 19811893Snikos.nikoleris@arm.com * @param addr the address to align. 19911893Snikos.nikoleris@arm.com * @return The block address. 20011893Snikos.nikoleris@arm.com */ 20111893Snikos.nikoleris@arm.com Addr blkAlign(Addr addr) const 20211893Snikos.nikoleris@arm.com { 20311893Snikos.nikoleris@arm.com return addr & ~blkMask; 20411893Snikos.nikoleris@arm.com } 20511893Snikos.nikoleris@arm.com 20611893Snikos.nikoleris@arm.com /** 20710815Sdavid.guillen@arm.com * Calculate the block offset of an address. 20810815Sdavid.guillen@arm.com * @param addr the address to get the offset of. 20910815Sdavid.guillen@arm.com * @return the block offset. 21010815Sdavid.guillen@arm.com */ 21110815Sdavid.guillen@arm.com int extractBlkOffset(Addr addr) const 21210815Sdavid.guillen@arm.com { 21311893Snikos.nikoleris@arm.com return (addr & blkMask); 21410815Sdavid.guillen@arm.com } 21510815Sdavid.guillen@arm.com 21610941Sdavid.guillen@arm.com /** 21710941Sdavid.guillen@arm.com * Find the cache block given set and way 21810941Sdavid.guillen@arm.com * @param set The set of the block. 21910941Sdavid.guillen@arm.com * @param way The way of the block. 22010941Sdavid.guillen@arm.com * @return The cache block. 22110941Sdavid.guillen@arm.com */ 22210941Sdavid.guillen@arm.com virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0; 22310941Sdavid.guillen@arm.com 22410941Sdavid.guillen@arm.com /** 22510941Sdavid.guillen@arm.com * Limit the allocation for the cache ways. 22610941Sdavid.guillen@arm.com * @param ways The maximum number of ways available for replacement. 22710941Sdavid.guillen@arm.com */ 22810941Sdavid.guillen@arm.com virtual void setWayAllocationMax(int ways) 22910941Sdavid.guillen@arm.com { 23010941Sdavid.guillen@arm.com panic("This tag class does not implement way allocation limit!\n"); 23110941Sdavid.guillen@arm.com } 23210941Sdavid.guillen@arm.com 23310941Sdavid.guillen@arm.com /** 23410941Sdavid.guillen@arm.com * Get the way allocation mask limit. 23510941Sdavid.guillen@arm.com * @return The maximum number of ways available for replacement. 23610941Sdavid.guillen@arm.com */ 23710941Sdavid.guillen@arm.com virtual int getWayAllocationMax() const 23810941Sdavid.guillen@arm.com { 23910941Sdavid.guillen@arm.com panic("This tag class does not implement way allocation limit!\n"); 24010941Sdavid.guillen@arm.com return -1; 24110941Sdavid.guillen@arm.com } 24210941Sdavid.guillen@arm.com 24312566Snikos.nikoleris@arm.com /** 24412566Snikos.nikoleris@arm.com * This function updates the tags when a block is invalidated but 24512566Snikos.nikoleris@arm.com * does not invalidate the block itself. 24612566Snikos.nikoleris@arm.com * @param blk The block to invalidate. 24712566Snikos.nikoleris@arm.com */ 24812566Snikos.nikoleris@arm.com virtual void invalidate(CacheBlk *blk) 24912566Snikos.nikoleris@arm.com { 25012566Snikos.nikoleris@arm.com assert(blk); 25112566Snikos.nikoleris@arm.com assert(blk->isValid()); 25212566Snikos.nikoleris@arm.com tagsInUse--; 25312566Snikos.nikoleris@arm.com occupancies[blk->srcMasterId]--; 25412566Snikos.nikoleris@arm.com } 25510815Sdavid.guillen@arm.com 25612600Sodanrc@yahoo.com.br /** 25712600Sodanrc@yahoo.com.br * Find replacement victim based on address. 25812600Sodanrc@yahoo.com.br * 25912600Sodanrc@yahoo.com.br * @param addr Address to find a victim for. 26012600Sodanrc@yahoo.com.br * @return Cache block to be replaced. 26112600Sodanrc@yahoo.com.br */ 26212600Sodanrc@yahoo.com.br virtual CacheBlk* findVictim(Addr addr) = 0; 26312600Sodanrc@yahoo.com.br 26411870Snikos.nikoleris@arm.com virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0; 26510815Sdavid.guillen@arm.com 26610815Sdavid.guillen@arm.com virtual Addr extractTag(Addr addr) const = 0; 26710815Sdavid.guillen@arm.com 26812636Sodanrc@yahoo.com.br /** 26912636Sodanrc@yahoo.com.br * Insert the new block into the cache and update stats. 27012636Sodanrc@yahoo.com.br * 27112636Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 27212636Sodanrc@yahoo.com.br * @param blk The block to update. 27312636Sodanrc@yahoo.com.br */ 27412636Sodanrc@yahoo.com.br virtual void insertBlock(PacketPtr pkt, CacheBlk *blk); 27510815Sdavid.guillen@arm.com 27612574Sodanrc@yahoo.com.br /** 27712574Sodanrc@yahoo.com.br * Regenerate the block address. 27812574Sodanrc@yahoo.com.br * 27912574Sodanrc@yahoo.com.br * @param block The block. 28012574Sodanrc@yahoo.com.br * @return the block address. 28112574Sodanrc@yahoo.com.br */ 28212574Sodanrc@yahoo.com.br virtual Addr regenerateBlkAddr(const CacheBlk* blk) const = 0; 28310815Sdavid.guillen@arm.com 28410815Sdavid.guillen@arm.com virtual int extractSet(Addr addr) const = 0; 28510815Sdavid.guillen@arm.com 28610815Sdavid.guillen@arm.com virtual void forEachBlk(CacheBlkVisitor &visitor) = 0; 2872810SN/A}; 2882810SN/A 2892810SN/Aclass BaseTagsCallback : public Callback 2902810SN/A{ 2912810SN/A BaseTags *tags; 2922810SN/A public: 2932810SN/A BaseTagsCallback(BaseTags *t) : tags(t) {} 2942810SN/A virtual void process() { tags->cleanupRefs(); }; 2952810SN/A}; 2962810SN/A 29710024Sdam.sunwoo@arm.comclass BaseTagsDumpCallback : public Callback 29810024Sdam.sunwoo@arm.com{ 29910024Sdam.sunwoo@arm.com BaseTags *tags; 30010024Sdam.sunwoo@arm.com public: 30110024Sdam.sunwoo@arm.com BaseTagsDumpCallback(BaseTags *t) : tags(t) {} 30210024Sdam.sunwoo@arm.com virtual void process() { tags->computeStats(); }; 30310024Sdam.sunwoo@arm.com}; 30410024Sdam.sunwoo@arm.com 30512492Sodanrc@yahoo.com.br#endif //__MEM_CACHE_TAGS_BASE_HH__ 306