base.cc revision 13225:8d1621fc586e 
1/*
2 * Copyright (c) 2013,2016,2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include <cassert>
52
53#include "base/types.hh"
54#include "mem/cache/base.hh"
55#include "mem/cache/replacement_policies/replaceable_entry.hh"
56#include "mem/cache/tags/indexing_policies/base.hh"
57#include "mem/request.hh"
58#include "sim/core.hh"
59#include "sim/sim_exit.hh"
60#include "sim/system.hh"
61
62BaseTags::BaseTags(const Params *p)
63    : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
64      size(p->size),
65      lookupLatency(p->tag_latency),
66      accessLatency(p->sequential_access ?
67                    p->tag_latency + p->data_latency :
68                    std::max(p->tag_latency, p->data_latency)),
69      cache(nullptr), indexingPolicy(p->indexing_policy),
70      warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
71      warmedUp(false), numBlocks(p->size / p->block_size),
72      dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
73{
74}
75
76void
77BaseTags::setCache(BaseCache *_cache)
78{
79    assert(!cache);
80    cache = _cache;
81}
82
83ReplaceableEntry*
84BaseTags::findBlockBySetAndWay(int set, int way) const
85{
86    return indexingPolicy->getEntry(set, way);
87}
88
89CacheBlk*
90BaseTags::findBlock(Addr addr, bool is_secure) const
91{
92    // Extract block tag
93    Addr tag = extractTag(addr);
94
95    // Find possible entries that may contain the given address
96    const std::vector<ReplaceableEntry*> entries =
97        indexingPolicy->getPossibleEntries(addr);
98
99    // Search for block
100    for (const auto& location : entries) {
101        CacheBlk* blk = static_cast<CacheBlk*>(location);
102        if ((blk->tag == tag) && blk->isValid() &&
103            (blk->isSecure() == is_secure)) {
104            return blk;
105        }
106    }
107
108    // Did not find block
109    return nullptr;
110}
111
112void
113BaseTags::insertBlock(const Addr addr, const bool is_secure,
114                      const int src_master_ID, const uint32_t task_ID,
115                      CacheBlk *blk)
116{
117    assert(!blk->isValid());
118
119    // Previous block, if existed, has been removed, and now we have
120    // to insert the new one
121    // Deal with what we are bringing in
122    assert(src_master_ID < cache->system->maxMasters());
123    occupancies[src_master_ID]++;
124
125    // Insert block with tag, src master id and task id
126    blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID);
127
128    // Check if cache warm up is done
129    if (!warmedUp && tagsInUse.value() >= warmupBound) {
130        warmedUp = true;
131        warmupCycle = curTick();
132    }
133
134    // We only need to write into one tag and one data block.
135    tagAccesses += 1;
136    dataAccesses += 1;
137}
138
139Addr
140BaseTags::extractTag(const Addr addr) const
141{
142    return indexingPolicy->extractTag(addr);
143}
144
145void
146BaseTags::cleanupRefsVisitor(CacheBlk &blk)
147{
148    if (blk.isValid()) {
149        totalRefs += blk.refCount;
150        ++sampledRefs;
151    }
152}
153
154void
155BaseTags::cleanupRefs()
156{
157    forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); });
158}
159
160void
161BaseTags::computeStatsVisitor(CacheBlk &blk)
162{
163    if (blk.isValid()) {
164        assert(blk.task_id < ContextSwitchTaskId::NumTaskId);
165        occupanciesTaskId[blk.task_id]++;
166        assert(blk.tickInserted <= curTick());
167        Tick age = curTick() - blk.tickInserted;
168
169        int age_index;
170        if (age / SimClock::Int::us < 10) { // <10us
171            age_index = 0;
172        } else if (age / SimClock::Int::us < 100) { // <100us
173            age_index = 1;
174        } else if (age / SimClock::Int::ms < 1) { // <1ms
175            age_index = 2;
176        } else if (age / SimClock::Int::ms < 10) { // <10ms
177            age_index = 3;
178        } else
179            age_index = 4; // >10ms
180
181        ageTaskId[blk.task_id][age_index]++;
182    }
183}
184
185void
186BaseTags::computeStats()
187{
188    for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) {
189        occupanciesTaskId[i] = 0;
190        for (unsigned j = 0; j < 5; ++j) {
191            ageTaskId[i][j] = 0;
192        }
193    }
194
195    forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); });
196}
197
198std::string
199BaseTags::print()
200{
201    std::string str;
202
203    auto print_blk = [&str](CacheBlk &blk) {
204        if (blk.isValid())
205            str += csprintf("\tBlock: %s\n", blk.print());
206    };
207    forEachBlk(print_blk);
208
209    if (str.empty())
210        str = "no valid tags\n";
211
212    return str;
213}
214
215void
216BaseTags::regStats()
217{
218    ClockedObject::regStats();
219
220    using namespace Stats;
221
222    tagsInUse
223        .name(name() + ".tagsinuse")
224        .desc("Cycle average of tags in use")
225        ;
226
227    totalRefs
228        .name(name() + ".total_refs")
229        .desc("Total number of references to valid blocks.")
230        ;
231
232    sampledRefs
233        .name(name() + ".sampled_refs")
234        .desc("Sample count of references to valid blocks.")
235        ;
236
237    avgRefs
238        .name(name() + ".avg_refs")
239        .desc("Average number of references to valid blocks.")
240        ;
241
242    avgRefs = totalRefs/sampledRefs;
243
244    warmupCycle
245        .name(name() + ".warmup_cycle")
246        .desc("Cycle when the warmup percentage was hit.")
247        ;
248
249    occupancies
250        .init(cache->system->maxMasters())
251        .name(name() + ".occ_blocks")
252        .desc("Average occupied blocks per requestor")
253        .flags(nozero | nonan)
254        ;
255    for (int i = 0; i < cache->system->maxMasters(); i++) {
256        occupancies.subname(i, cache->system->getMasterName(i));
257    }
258
259    avgOccs
260        .name(name() + ".occ_percent")
261        .desc("Average percentage of cache occupancy")
262        .flags(nozero | total)
263        ;
264    for (int i = 0; i < cache->system->maxMasters(); i++) {
265        avgOccs.subname(i, cache->system->getMasterName(i));
266    }
267
268    avgOccs = occupancies / Stats::constant(numBlocks);
269
270    occupanciesTaskId
271        .init(ContextSwitchTaskId::NumTaskId)
272        .name(name() + ".occ_task_id_blocks")
273        .desc("Occupied blocks per task id")
274        .flags(nozero | nonan)
275        ;
276
277    ageTaskId
278        .init(ContextSwitchTaskId::NumTaskId, 5)
279        .name(name() + ".age_task_id_blocks")
280        .desc("Occupied blocks per task id")
281        .flags(nozero | nonan)
282        ;
283
284    percentOccsTaskId
285        .name(name() + ".occ_task_id_percent")
286        .desc("Percentage of cache occupancy per task id")
287        .flags(nozero)
288        ;
289
290    percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
291
292    tagAccesses
293        .name(name() + ".tag_accesses")
294        .desc("Number of tag accesses")
295        ;
296
297    dataAccesses
298        .name(name() + ".data_accesses")
299        .desc("Number of data accesses")
300        ;
301
302    registerDumpCallback(new BaseTagsDumpCallback(this));
303    registerExitCallback(new BaseTagsCallback(this));
304}
305