base.cc revision 12745:e28c117a9806
1/* 2 * Copyright (c) 2013,2016,2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Ron Dreslinski 42 */ 43 44/** 45 * @file 46 * Definitions of BaseTags. 47 */ 48 49#include "mem/cache/tags/base.hh" 50 51#include <cassert> 52 53#include "base/types.hh" 54#include "mem/cache/base.hh" 55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "sim/core.hh" 58#include "sim/sim_exit.hh" 59#include "sim/system.hh" 60 61BaseTags::BaseTags(const Params *p) 62 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), 63 size(p->size), 64 lookupLatency(p->tag_latency), 65 accessLatency(p->sequential_access ? 66 p->tag_latency + p->data_latency : 67 std::max(p->tag_latency, p->data_latency)), 68 cache(nullptr), 69 warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)), 70 warmedUp(false), numBlocks(p->size / p->block_size), 71 dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk 72{ 73} 74 75void 76BaseTags::setCache(BaseCache *_cache) 77{ 78 assert(!cache); 79 cache = _cache; 80} 81 82void 83BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk) 84{ 85 assert(!blk->isValid()); 86 87 // Get address 88 Addr addr = pkt->getAddr(); 89 90 // Previous block, if existed, has been removed, and now we have 91 // to insert the new one 92 93 // Deal with what we are bringing in 94 MasterID master_id = pkt->req->masterId(); 95 assert(master_id < cache->system->maxMasters()); 96 occupancies[master_id]++; 97 98 // Insert block with tag, src master id and task id 99 blk->insert(extractTag(addr), pkt->isSecure(), master_id, 100 pkt->req->taskId()); 101 102 if (!warmedUp && tagsInUse.value() >= warmupBound) { 103 warmedUp = true; 104 warmupCycle = curTick(); 105 } 106 107 // We only need to write into one tag and one data block. 108 tagAccesses += 1; 109 dataAccesses += 1; 110} 111 112void 113BaseTags::cleanupRefsVisitor(CacheBlk &blk) 114{ 115 if (blk.isValid()) { 116 totalRefs += blk.refCount; 117 ++sampledRefs; 118 } 119} 120 121void 122BaseTags::cleanupRefs() 123{ 124 forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); }); 125} 126 127void 128BaseTags::computeStatsVisitor(CacheBlk &blk) 129{ 130 if (blk.isValid()) { 131 assert(blk.task_id < ContextSwitchTaskId::NumTaskId); 132 occupanciesTaskId[blk.task_id]++; 133 assert(blk.tickInserted <= curTick()); 134 Tick age = curTick() - blk.tickInserted; 135 136 int age_index; 137 if (age / SimClock::Int::us < 10) { // <10us 138 age_index = 0; 139 } else if (age / SimClock::Int::us < 100) { // <100us 140 age_index = 1; 141 } else if (age / SimClock::Int::ms < 1) { // <1ms 142 age_index = 2; 143 } else if (age / SimClock::Int::ms < 10) { // <10ms 144 age_index = 3; 145 } else 146 age_index = 4; // >10ms 147 148 ageTaskId[blk.task_id][age_index]++; 149 } 150} 151 152void 153BaseTags::computeStats() 154{ 155 for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) { 156 occupanciesTaskId[i] = 0; 157 for (unsigned j = 0; j < 5; ++j) { 158 ageTaskId[i][j] = 0; 159 } 160 } 161 162 forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); }); 163} 164 165std::string 166BaseTags::print() 167{ 168 std::string str; 169 170 auto print_blk = [&str](CacheBlk &blk) { 171 if (blk.isValid()) 172 str += csprintf("\tset: %d way: %d %s\n", blk.set, blk.way, 173 blk.print()); 174 }; 175 forEachBlk(print_blk); 176 177 if (str.empty()) 178 str = "no valid tags\n"; 179 180 return str; 181} 182 183void 184BaseTags::regStats() 185{ 186 ClockedObject::regStats(); 187 188 using namespace Stats; 189 190 tagsInUse 191 .name(name() + ".tagsinuse") 192 .desc("Cycle average of tags in use") 193 ; 194 195 totalRefs 196 .name(name() + ".total_refs") 197 .desc("Total number of references to valid blocks.") 198 ; 199 200 sampledRefs 201 .name(name() + ".sampled_refs") 202 .desc("Sample count of references to valid blocks.") 203 ; 204 205 avgRefs 206 .name(name() + ".avg_refs") 207 .desc("Average number of references to valid blocks.") 208 ; 209 210 avgRefs = totalRefs/sampledRefs; 211 212 warmupCycle 213 .name(name() + ".warmup_cycle") 214 .desc("Cycle when the warmup percentage was hit.") 215 ; 216 217 occupancies 218 .init(cache->system->maxMasters()) 219 .name(name() + ".occ_blocks") 220 .desc("Average occupied blocks per requestor") 221 .flags(nozero | nonan) 222 ; 223 for (int i = 0; i < cache->system->maxMasters(); i++) { 224 occupancies.subname(i, cache->system->getMasterName(i)); 225 } 226 227 avgOccs 228 .name(name() + ".occ_percent") 229 .desc("Average percentage of cache occupancy") 230 .flags(nozero | total) 231 ; 232 for (int i = 0; i < cache->system->maxMasters(); i++) { 233 avgOccs.subname(i, cache->system->getMasterName(i)); 234 } 235 236 avgOccs = occupancies / Stats::constant(numBlocks); 237 238 occupanciesTaskId 239 .init(ContextSwitchTaskId::NumTaskId) 240 .name(name() + ".occ_task_id_blocks") 241 .desc("Occupied blocks per task id") 242 .flags(nozero | nonan) 243 ; 244 245 ageTaskId 246 .init(ContextSwitchTaskId::NumTaskId, 5) 247 .name(name() + ".age_task_id_blocks") 248 .desc("Occupied blocks per task id") 249 .flags(nozero | nonan) 250 ; 251 252 percentOccsTaskId 253 .name(name() + ".occ_task_id_percent") 254 .desc("Percentage of cache occupancy per task id") 255 .flags(nozero) 256 ; 257 258 percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks); 259 260 tagAccesses 261 .name(name() + ".tag_accesses") 262 .desc("Number of tag accesses") 263 ; 264 265 dataAccesses 266 .name(name() + ".data_accesses") 267 .desc("Number of data accesses") 268 ; 269 270 registerDumpCallback(new BaseTagsDumpCallback(this)); 271 registerExitCallback(new BaseTagsCallback(this)); 272} 273