stride.hh revision 2810
1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ron Dreslinski 29 */ 30 31/** 32 * @file 33 * Describes a strided prefetcher based on template policies. 34 */ 35 36#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ 37#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ 38 39#include "base/misc.hh" // fatal, panic, and warn 40 41#include "mem/cache/prefetch/prefetcher.hh" 42 43/** 44 * A template-policy based cache. The behavior of the cache can be altered by 45 * supplying different template policies. TagStore handles all tag and data 46 * storage @sa TagStore. Buffering handles all misses and writes/writebacks 47 * @sa MissQueue. Coherence handles all coherence policy details @sa 48 * UniCoherence, SimpleMultiCoherence. 49 */ 50template <class TagStore, class Buffering> 51class StridePrefetcher : public Prefetcher<TagStore, Buffering> 52{ 53 protected: 54 55 Buffering* mq; 56 TagStore* tags; 57 58 class strideEntry 59 { 60 public: 61 Addr IAddr; 62 Addr MAddr; 63 int stride; 64 int64_t confidence; 65 66/* bool operator < (strideEntry a,strideEntry b) 67 { 68 if (a.confidence == b.confidence) { 69 return true; //?????? 70 } 71 else return a.confidence < b.confidence; 72 }*/ 73 }; 74 Addr* lastMissAddr[64/*MAX_CPUS*/]; 75 76 std::list<strideEntry*> table[64/*MAX_CPUS*/]; 77 Tick latency; 78 int degree; 79 bool useCPUId; 80 81 82 public: 83 84 StridePrefetcher(int size, bool pageStop, bool serialSquash, 85 bool cacheCheckPush, bool onlyData, 86 Tick latency, int degree, bool useCPUId) 87 :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash, 88 cacheCheckPush, onlyData), 89 latency(latency), degree(degree), useCPUId(useCPUId) 90 { 91 } 92 93 ~StridePrefetcher() {} 94 95 void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses, 96 std::list<Tick> &delays) 97 { 98// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1); 99 int cpuID = pkt->cpu_num; 100 if (!useCPUId) cpuID = 0; 101 102 /* Scan Table for IAddr Match */ 103/* std::list<strideEntry*>::iterator iter; 104 for (iter=table[cpuID].begin(); 105 iter !=table[cpuID].end(); 106 iter++) { 107 if ((*iter)->IAddr == pkt->pc) break; 108 } 109 110 if (iter != table[cpuID].end()) { 111 //Hit in table 112 113 int newStride = blkAddr - (*iter)->MAddr; 114 if (newStride == (*iter)->stride) { 115 (*iter)->confidence++; 116 } 117 else { 118 (*iter)->stride = newStride; 119 (*iter)->confidence--; 120 } 121 122 (*iter)->MAddr = blkAddr; 123 124 for (int d=1; d <= degree; d++) { 125 Addr newAddr = blkAddr + d * newStride; 126 if (this->pageStop && 127 (blkAddr & ~(TheISA::VMPageSize - 1)) != 128 (newAddr & ~(TheISA::VMPageSize - 1))) 129 { 130 //Spanned the page, so now stop 131 this->pfSpanPage += degree - d + 1; 132 return; 133 } 134 else 135 { 136 addresses.push_back(newAddr); 137 delays.push_back(latency); 138 } 139 } 140 } 141 else { 142 //Miss in table 143 //Find lowest confidence and replace 144 145 } 146*/ } 147}; 148 149#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ 150