stride.hh revision 10623
12810SN/A/* 210028SGiacomo.Gabrielli@arm.com * Copyright (c) 2012-2013 ARM Limited 310028SGiacomo.Gabrielli@arm.com * All rights reserved 410028SGiacomo.Gabrielli@arm.com * 510028SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 610028SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 710028SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 810028SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 910028SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1010028SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1110028SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1210028SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1310028SGiacomo.Gabrielli@arm.com * 142810SN/A * Copyright (c) 2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Ron Dreslinski 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 453861SN/A * Describes a strided prefetcher. 462810SN/A */ 472810SN/A 4810623Smitch.hayenga@arm.com#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__ 4910623Smitch.hayenga@arm.com#define __MEM_CACHE_PREFETCH_STRIDE_HH__ 502810SN/A 5110623Smitch.hayenga@arm.com#include "mem/cache/prefetch/queued.hh" 528831Smrinmoy.ghosh@arm.com#include "params/StridePrefetcher.hh" 532810SN/A 5410623Smitch.hayenga@arm.comclass StridePrefetcher : public QueuedPrefetcher 552810SN/A{ 562810SN/A protected: 5710623Smitch.hayenga@arm.com static const int maxContexts = 64; 582810SN/A 5910623Smitch.hayenga@arm.com const int maxConf; 6010623Smitch.hayenga@arm.com const int threshConf; 6110623Smitch.hayenga@arm.com const int minConf; 6210623Smitch.hayenga@arm.com const int startConf; 635875Ssteve.reinhardt@amd.com 6410623Smitch.hayenga@arm.com const int pcTableAssoc; 6510623Smitch.hayenga@arm.com const int pcTableSets; 665875Ssteve.reinhardt@amd.com 6710623Smitch.hayenga@arm.com const bool useMasterId; 6810623Smitch.hayenga@arm.com 6910623Smitch.hayenga@arm.com const int degree; 7010623Smitch.hayenga@arm.com 7110623Smitch.hayenga@arm.com struct StrideEntry 722810SN/A { 7310623Smitch.hayenga@arm.com StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0), 7410623Smitch.hayenga@arm.com confidence(0) 7510623Smitch.hayenga@arm.com { } 7610623Smitch.hayenga@arm.com 775875Ssteve.reinhardt@amd.com Addr instAddr; 7810623Smitch.hayenga@arm.com Addr lastAddr; 7910028SGiacomo.Gabrielli@arm.com bool isSecure; 802810SN/A int stride; 815875Ssteve.reinhardt@amd.com int confidence; 825875Ssteve.reinhardt@amd.com }; 832810SN/A 8410623Smitch.hayenga@arm.com StrideEntry **pcTable[maxContexts]; 852810SN/A 8610623Smitch.hayenga@arm.com bool pcTableHit(Addr pc, bool is_secure, int master_id, StrideEntry* &entry); 8710623Smitch.hayenga@arm.com StrideEntry* pcTableVictim(Addr pc, int master_id); 8810053Smitch.hayenga+gem5@gmail.com 8910623Smitch.hayenga@arm.com Addr pcHash(Addr pc) const; 902810SN/A public: 912810SN/A 9210623Smitch.hayenga@arm.com StridePrefetcher(const StridePrefetcherParams *p); 9310623Smitch.hayenga@arm.com ~StridePrefetcher(); 942810SN/A 9510623Smitch.hayenga@arm.com void calculatePrefetch(const PacketPtr &pkt, std::vector<Addr> &addresses); 962810SN/A}; 972810SN/A 9810623Smitch.hayenga@arm.com#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__ 99