base.hh revision 6665:874f2ee2f115 
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Miss and writeback queue declarations.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43#include "params/BaseCache.hh"
44
45class BaseCache;
46
47class BasePrefetcher
48{
49  protected:
50
51    /** The Prefetch Queue. */
52    std::list<PacketPtr> pf;
53
54    // PARAMETERS
55
56    /** The number of MSHRs in the Prefetch Queue. */
57    const unsigned size;
58
59    /** Pointr to the parent cache. */
60    BaseCache* cache;
61
62    /** The block size of the parent cache. */
63    int blkSize;
64
65    /** Do we prefetch across page boundaries. */
66    bool pageStop;
67
68    /** Do we remove prefetches with later times than a new miss.*/
69    bool serialSquash;
70
71    /** Do we prefetch on only data reads, or on inst reads as well. */
72    bool onlyData;
73
74    std::string _name;
75
76  public:
77
78    Stats::Scalar pfIdentified;
79    Stats::Scalar pfMSHRHit;
80    Stats::Scalar pfCacheHit;
81    Stats::Scalar pfBufferHit;
82    Stats::Scalar pfRemovedFull;
83    Stats::Scalar pfRemovedMSHR;
84    Stats::Scalar pfIssued;
85    Stats::Scalar pfSpanPage;
86    Stats::Scalar pfSquashed;
87
88    void regStats(const std::string &name);
89
90  public:
91
92    BasePrefetcher(const BaseCacheParams *p);
93
94    virtual ~BasePrefetcher() {}
95
96    const std::string name() const { return _name; }
97
98    void setCache(BaseCache *_cache);
99
100    /**
101     * Notify prefetcher of cache access (may be any access or just
102     * misses, depending on cache parameters.)
103     * @retval Time of next prefetch availability, or 0 if none.
104     */
105    Tick notify(PacketPtr &pkt, Tick time);
106
107    bool inCache(Addr addr);
108
109    bool inMissQueue(Addr addr);
110
111    PacketPtr getPacket();
112
113    bool havePending()
114    {
115        return !pf.empty();
116    }
117
118    Tick nextPrefetchReadyTime()
119    {
120        return pf.empty() ? MaxTick : pf.front()->time;
121    }
122
123    virtual void calculatePrefetch(PacketPtr &pkt,
124                                   std::list<Addr> &addresses,
125                                   std::list<Tick> &delays) = 0;
126
127    std::list<PacketPtr>::iterator inPrefetch(Addr address);
128
129    /**
130     * Utility function: are addresses a and b on the same VM page?
131     */
132    bool samePage(Addr a, Addr b);
133};
134
135
136#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
137