base.hh revision 13991:102d94094d6b 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include <cstdint>
53
54#include "arch/isa_traits.hh"
55#include "base/statistics.hh"
56#include "base/types.hh"
57#include "mem/packet.hh"
58#include "mem/request.hh"
59#include "sim/byteswap.hh"
60#include "sim/clocked_object.hh"
61#include "sim/probe/probe.hh"
62
63class BaseCache;
64struct BasePrefetcherParams;
65
66class BasePrefetcher : public ClockedObject
67{
68    class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
69    {
70      public:
71        PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
72                         const std::string &name, bool _isFill = false,
73                         bool _miss = false)
74            : ProbeListenerArgBase(pm, name),
75              parent(_parent), isFill(_isFill), miss(_miss) {}
76        void notify(const PacketPtr &pkt) override;
77      protected:
78        BasePrefetcher &parent;
79        const bool isFill;
80        const bool miss;
81    };
82
83    std::vector<PrefetchListener *> listeners;
84
85  public:
86
87    /**
88     * Class containing the information needed by the prefetch to train and
89     * generate new prefetch requests.
90     */
91    class PrefetchInfo {
92        /** The address used to train and generate prefetches */
93        Addr address;
94        /** The program counter that generated this address. */
95        Addr pc;
96        /** The requestor ID that generated this address. */
97        MasterID masterId;
98        /** Validity bit for the PC of this address. */
99        bool validPC;
100        /** Whether this address targets the secure memory space. */
101        bool secure;
102        /** Size in bytes of the request triggering this event */
103        unsigned int size;
104        /** Whether this event comes from a write request */
105        bool write;
106        /** Physical address, needed because address can be virtual */
107        Addr paddress;
108        /** Whether this event comes from a cache miss */
109        bool cacheMiss;
110        /** Pointer to the associated request data */
111        uint8_t *data;
112
113      public:
114        /**
115         * Obtains the address value of this Prefetcher address.
116         * @return the addres value.
117         */
118        Addr getAddr() const
119        {
120            return address;
121        }
122
123        /**
124         * Returns true if the address targets the secure memory space.
125         * @return true if the address targets the secure memory space.
126         */
127        bool isSecure() const
128        {
129            return secure;
130        }
131
132        /**
133         * Returns the program counter that generated this request.
134         * @return the pc value
135         */
136        Addr getPC() const
137        {
138            assert(hasPC());
139            return pc;
140        }
141
142        /**
143         * Returns true if the associated program counter is valid
144         * @return true if the program counter has a valid value
145         */
146        bool hasPC() const
147        {
148            return validPC;
149        }
150
151        /**
152         * Gets the requestor ID that generated this address
153         * @return the requestor ID that generated this address
154         */
155        MasterID getMasterId() const
156        {
157            return masterId;
158        }
159
160        /**
161         * Gets the size of the request triggering this event
162         * @return the size in bytes of the request triggering this event
163         */
164        unsigned int getSize() const
165        {
166            return size;
167        }
168
169        /**
170         * Checks if the request that caused this prefetch event was a write
171         * request
172         * @return true if the request causing this event is a write request
173         */
174        bool isWrite() const
175        {
176            return write;
177        }
178
179        /**
180         * Gets the physical address of the request
181         * @return physical address of the request
182         */
183        Addr getPaddr() const
184        {
185            return paddress;
186        }
187
188        /**
189         * Check if this event comes from a cache miss
190         * @result true if this event comes from a cache miss
191         */
192        bool isCacheMiss() const
193        {
194            return cacheMiss;
195        }
196
197        /**
198         * Gets the associated data of the request triggering the event
199         * @param Byte ordering of the stored data
200         * @return the data
201         */
202        template <typename T>
203        inline T
204        get(ByteOrder endian) const
205        {
206            if (data == nullptr) {
207                panic("PrefetchInfo::get called with a request with no data.");
208            }
209            switch (endian) {
210                case BigEndianByteOrder:
211                    return betoh(*(T*)data);
212
213                case LittleEndianByteOrder:
214                    return letoh(*(T*)data);
215
216                default:
217                    panic("Illegal byte order in PrefetchInfo::get()\n");
218            };
219        }
220
221        /**
222         * Check for equality
223         * @param pfi PrefetchInfo to compare against
224         * @return True if this object and the provided one are equal
225         */
226        bool sameAddr(PrefetchInfo const &pfi) const
227        {
228            return this->getAddr() == pfi.getAddr() &&
229                this->isSecure() == pfi.isSecure();
230        }
231
232        /**
233         * Constructs a PrefetchInfo using a PacketPtr.
234         * @param pkt PacketPtr used to generate the PrefetchInfo
235         * @param addr the address value of the new object, this address is
236         *        used to train the prefetcher
237         * @param miss whether this event comes from a cache miss
238         */
239        PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
240
241        /**
242         * Constructs a PrefetchInfo using a new address value and
243         * another PrefetchInfo as a reference.
244         * @param pfi PrefetchInfo used to generate this new object
245         * @param addr the address value of the new object
246         */
247        PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
248
249        ~PrefetchInfo()
250        {
251            delete data;
252        }
253    };
254
255  protected:
256
257    // PARAMETERS
258
259    /** Pointr to the parent cache. */
260    BaseCache* cache;
261
262    /** The block size of the parent cache. */
263    unsigned blkSize;
264
265    /** log_2(block size of the parent cache). */
266    unsigned lBlkSize;
267
268    /** Only consult prefetcher on cache misses? */
269    const bool onMiss;
270
271    /** Consult prefetcher on reads? */
272    const bool onRead;
273
274    /** Consult prefetcher on reads? */
275    const bool onWrite;
276
277    /** Consult prefetcher on data accesses? */
278    const bool onData;
279
280    /** Consult prefetcher on instruction accesses? */
281    const bool onInst;
282
283    /** Request id for prefetches */
284    const MasterID masterId;
285
286    const Addr pageBytes;
287
288    /** Prefetch on every access, not just misses */
289    const bool prefetchOnAccess;
290
291    /** Use Virtual Addresses for prefetching */
292    const bool useVirtualAddresses;
293
294    /**
295     * Determine if this access should be observed
296     * @param pkt The memory request causing the event
297     * @param miss whether this event comes from a cache miss
298     */
299    bool observeAccess(const PacketPtr &pkt, bool miss) const;
300
301    /** Determine if address is in cache */
302    bool inCache(Addr addr, bool is_secure) const;
303
304    /** Determine if address is in cache miss queue */
305    bool inMissQueue(Addr addr, bool is_secure) const;
306
307    bool hasBeenPrefetched(Addr addr, bool is_secure) const;
308
309    /** Determine if addresses are on the same page */
310    bool samePage(Addr a, Addr b) const;
311    /** Determine the address of the block in which a lays */
312    Addr blockAddress(Addr a) const;
313    /** Determine the address of a at block granularity */
314    Addr blockIndex(Addr a) const;
315    /** Determine the address of the page in which a lays */
316    Addr pageAddress(Addr a) const;
317    /** Determine the page-offset of a  */
318    Addr pageOffset(Addr a) const;
319    /** Build the address of the i-th block inside the page */
320    Addr pageIthBlockAddress(Addr page, uint32_t i) const;
321
322    Stats::Scalar pfIssued;
323
324    /** Total prefetches issued */
325    uint64_t issuedPrefetches;
326    /** Total prefetches that has been useful */
327    uint64_t usefulPrefetches;
328
329  public:
330
331    BasePrefetcher(const BasePrefetcherParams *p);
332
333    virtual ~BasePrefetcher() {}
334
335    virtual void setCache(BaseCache *_cache);
336
337    /**
338     * Notify prefetcher of cache access (may be any access or just
339     * misses, depending on cache parameters.)
340     */
341    virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
342
343    /** Notify prefetcher of cache fill */
344    virtual void notifyFill(const PacketPtr &pkt)
345    {}
346
347    virtual PacketPtr getPacket() = 0;
348
349    virtual Tick nextPrefetchReadyTime() const = 0;
350
351    /**
352     * Register local statistics.
353     */
354    void regStats() override;
355
356    /**
357     * Register probe points for this object.
358     */
359    void regProbeListeners() override;
360
361    /**
362     * Process a notification event from the ProbeListener.
363     * @param pkt The memory request causing the event
364     * @param miss whether this event comes from a cache miss
365     */
366    void probeNotify(const PacketPtr &pkt, bool miss);
367
368    /**
369     * Add a SimObject and a probe name to listen events from
370     * @param obj The SimObject pointer to listen from
371     * @param name The probe name
372     */
373    void addEventProbe(SimObject *obj, const char *name);
374};
375#endif //__MEM_CACHE_PREFETCH_BASE_HH__
376