base.hh revision 13717:11e81e2a98bd 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include <cstdint>
53
54#include "base/statistics.hh"
55#include "base/types.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58#include "sim/clocked_object.hh"
59#include "sim/probe/probe.hh"
60
61class BaseCache;
62struct BasePrefetcherParams;
63
64class BasePrefetcher : public ClockedObject
65{
66    class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
67    {
68      public:
69        PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
70                         const std::string &name, bool _isFill = false)
71            : ProbeListenerArgBase(pm, name),
72              parent(_parent), isFill(_isFill) {}
73        void notify(const PacketPtr &pkt) override;
74      protected:
75        BasePrefetcher &parent;
76        bool isFill;
77    };
78
79    std::vector<PrefetchListener *> listeners;
80
81  public:
82
83    /**
84     * Class containing the information needed by the prefetch to train and
85     * generate new prefetch requests.
86     */
87    class PrefetchInfo {
88        /** The address. */
89        Addr address;
90        /** The program counter that generated this address. */
91        Addr pc;
92        /** The requestor ID that generated this address. */
93        MasterID masterId;
94        /** Validity bit for the PC of this address. */
95        bool validPC;
96        /** Whether this address targets the secure memory space. */
97        bool secure;
98
99      public:
100        /**
101         * Obtains the address value of this Prefetcher address.
102         * @return the addres value.
103         */
104        Addr getAddr() const
105        {
106            return address;
107        }
108
109        /**
110         * Returns true if the address targets the secure memory space.
111         * @return true if the address targets the secure memory space.
112         */
113        bool isSecure() const
114        {
115            return secure;
116        }
117
118        /**
119         * Returns the program counter that generated this request.
120         * @return the pc value
121         */
122        Addr getPC() const
123        {
124            assert(hasPC());
125            return pc;
126        }
127
128        /**
129         * Returns true if the associated program counter is valid
130         * @return true if the program counter has a valid value
131         */
132        bool hasPC() const
133        {
134            return validPC;
135        }
136
137        /**
138         * Gets the requestor ID that generated this address
139         * @return the requestor ID that generated this address
140         */
141        MasterID getMasterId() const
142        {
143            return masterId;
144        }
145
146        /**
147         * Check for equality
148         * @param pfi PrefetchInfo to compare against
149         * @return True if this object and the provided one are equal
150         */
151        bool sameAddr(PrefetchInfo const &pfi) const
152        {
153            return this->getAddr() == pfi.getAddr() &&
154                this->isSecure() == pfi.isSecure();
155        }
156
157        /**
158         * Constructs a PrefetchInfo using a PacketPtr.
159         * @param pkt PacketPtr used to generate the PrefetchInfo
160         * @param addr the address value of the new object
161         */
162        PrefetchInfo(PacketPtr pkt, Addr addr);
163
164        /**
165         * Constructs a PrefetchInfo using a new address value and
166         * another PrefetchInfo as a reference.
167         * @param pfi PrefetchInfo used to generate this new object
168         * @param addr the address value of the new object
169         */
170        PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
171    };
172
173  protected:
174
175    // PARAMETERS
176
177    /** Pointr to the parent cache. */
178    BaseCache* cache;
179
180    /** The block size of the parent cache. */
181    unsigned blkSize;
182
183    /** log_2(block size of the parent cache). */
184    unsigned lBlkSize;
185
186    /** Only consult prefetcher on cache misses? */
187    const bool onMiss;
188
189    /** Consult prefetcher on reads? */
190    const bool onRead;
191
192    /** Consult prefetcher on reads? */
193    const bool onWrite;
194
195    /** Consult prefetcher on data accesses? */
196    const bool onData;
197
198    /** Consult prefetcher on instruction accesses? */
199    const bool onInst;
200
201    /** Request id for prefetches */
202    const MasterID masterId;
203
204    const Addr pageBytes;
205
206    /** Prefetch on every access, not just misses */
207    const bool prefetchOnAccess;
208
209    /** Use Virtual Addresses for prefetching */
210    const bool useVirtualAddresses;
211
212    /** Determine if this access should be observed */
213    bool observeAccess(const PacketPtr &pkt) const;
214
215    /** Determine if address is in cache */
216    bool inCache(Addr addr, bool is_secure) const;
217
218    /** Determine if address is in cache miss queue */
219    bool inMissQueue(Addr addr, bool is_secure) const;
220
221    bool hasBeenPrefetched(Addr addr, bool is_secure) const;
222
223    /** Determine if addresses are on the same page */
224    bool samePage(Addr a, Addr b) const;
225    /** Determine the address of the block in which a lays */
226    Addr blockAddress(Addr a) const;
227    /** Determine the address of a at block granularity */
228    Addr blockIndex(Addr a) const;
229    /** Determine the address of the page in which a lays */
230    Addr pageAddress(Addr a) const;
231    /** Determine the page-offset of a  */
232    Addr pageOffset(Addr a) const;
233    /** Build the address of the i-th block inside the page */
234    Addr pageIthBlockAddress(Addr page, uint32_t i) const;
235
236    Stats::Scalar pfIssued;
237
238    /** Total prefetches issued */
239    uint64_t issuedPrefetches;
240    /** Total prefetches that has been useful */
241    uint64_t usefulPrefetches;
242
243  public:
244
245    BasePrefetcher(const BasePrefetcherParams *p);
246
247    virtual ~BasePrefetcher() {}
248
249    void setCache(BaseCache *_cache);
250
251    /**
252     * Notify prefetcher of cache access (may be any access or just
253     * misses, depending on cache parameters.)
254     */
255    virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
256
257    /** Notify prefetcher of cache fill */
258    virtual void notifyFill(const PacketPtr &pkt)
259    {}
260
261    virtual PacketPtr getPacket() = 0;
262
263    virtual Tick nextPrefetchReadyTime() const = 0;
264
265    /**
266     * Register local statistics.
267     */
268    void regStats() override;
269
270    /**
271     * Register probe points for this object.
272     */
273    void regProbeListeners() override;
274
275    /**
276     * Process a notification event from the ProbeListener.
277     * @param pkt The memory request causing the event
278     */
279    void probeNotify(const PacketPtr &pkt);
280
281    /**
282     * Add a SimObject and a probe name to listen events from
283     * @param obj The SimObject pointer to listen from
284     * @param name The probe name
285     */
286    void addEventProbe(SimObject *obj, const char *name);
287};
288#endif //__MEM_CACHE_PREFETCH_BASE_HH__
289