base.hh revision 12727:56c23b54bcb1 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include <cstdint>
53
54#include "base/statistics.hh"
55#include "base/types.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58#include "sim/clocked_object.hh"
59
60class BaseCache;
61struct BasePrefetcherParams;
62class System;
63
64class BasePrefetcher : public ClockedObject
65{
66  protected:
67
68    // PARAMETERS
69
70    /** Pointr to the parent cache. */
71    BaseCache* cache;
72
73    /** The block size of the parent cache. */
74    unsigned blkSize;
75
76    /** log_2(block size of the parent cache). */
77    unsigned lBlkSize;
78
79    /** System we belong to */
80    System* system;
81
82    /** Only consult prefetcher on cache misses? */
83    bool onMiss;
84
85    /** Consult prefetcher on reads? */
86    bool onRead;
87
88    /** Consult prefetcher on reads? */
89    bool onWrite;
90
91    /** Consult prefetcher on data accesses? */
92    bool onData;
93
94    /** Consult prefetcher on instruction accesses? */
95    bool onInst;
96
97    /** Request id for prefetches */
98    MasterID masterId;
99
100    const Addr pageBytes;
101
102    /** Determine if this access should be observed */
103    bool observeAccess(const PacketPtr &pkt) const;
104
105    /** Determine if address is in cache */
106    bool inCache(Addr addr, bool is_secure) const;
107
108    /** Determine if address is in cache miss queue */
109    bool inMissQueue(Addr addr, bool is_secure) const;
110
111    /** Determine if addresses are on the same page */
112    bool samePage(Addr a, Addr b) const;
113    /** Determine the address of the block in which a lays */
114    Addr blockAddress(Addr a) const;
115    /** Determine the address of a at block granularity */
116    Addr blockIndex(Addr a) const;
117    /** Determine the address of the page in which a lays */
118    Addr pageAddress(Addr a) const;
119    /** Determine the page-offset of a  */
120    Addr pageOffset(Addr a) const;
121    /** Build the address of the i-th block inside the page */
122    Addr pageIthBlockAddress(Addr page, uint32_t i) const;
123
124
125    Stats::Scalar pfIssued;
126
127  public:
128
129    BasePrefetcher(const BasePrefetcherParams *p);
130
131    virtual ~BasePrefetcher() {}
132
133    virtual void setCache(BaseCache *_cache);
134
135    /**
136     * Notify prefetcher of cache access (may be any access or just
137     * misses, depending on cache parameters.)
138     * @retval Time of next prefetch availability, or MaxTick if none.
139     */
140    virtual Tick notify(const PacketPtr &pkt) = 0;
141
142    virtual PacketPtr getPacket() = 0;
143
144    virtual Tick nextPrefetchReadyTime() const = 0;
145
146    virtual void regStats();
147};
148#endif //__MEM_CACHE_PREFETCH_BASE_HH__
149