base.cc revision 12727 
112771Sqtt2@cornell.edu/*
212771Sqtt2@cornell.edu * Copyright (c) 2013-2014 ARM Limited
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412771Sqtt2@cornell.edu *
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812771Sqtt2@cornell.edu * to a hardware implementation of the functionality of the software
912771Sqtt2@cornell.edu * licensed hereunder.  You may use the software subject to the license
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1112771Sqtt2@cornell.edu * unmodified and in its entirety in all distributions of the software,
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1312771Sqtt2@cornell.edu *
1412771Sqtt2@cornell.edu * Copyright (c) 2005 The Regents of The University of Michigan
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3812771Sqtt2@cornell.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3912771Sqtt2@cornell.edu *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
54#include "mem/cache/base.hh"
55#include "params/BasePrefetcher.hh"
56#include "sim/system.hh"
57
58BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
59    : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
60      system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
61      onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
62      masterId(system->getMasterId(this)),
63      pageBytes(system->getPageBytes())
64{
65}
66
67void
68BasePrefetcher::setCache(BaseCache *_cache)
69{
70    assert(!cache);
71    cache = _cache;
72    blkSize = cache->getBlockSize();
73    lBlkSize = floorLog2(blkSize);
74}
75
76void
77BasePrefetcher::regStats()
78{
79    ClockedObject::regStats();
80
81    pfIssued
82        .name(name() + ".num_hwpf_issued")
83        .desc("number of hwpf issued")
84        ;
85
86}
87
88bool
89BasePrefetcher::observeAccess(const PacketPtr &pkt) const
90{
91    Addr addr = pkt->getAddr();
92    bool fetch = pkt->req->isInstFetch();
93    bool read = pkt->isRead();
94    bool inv = pkt->isInvalidate();
95    bool is_secure = pkt->isSecure();
96
97    if (pkt->req->isUncacheable()) return false;
98    if (fetch && !onInst) return false;
99    if (!fetch && !onData) return false;
100    if (!fetch && read && !onRead) return false;
101    if (!fetch && !read && !onWrite) return false;
102    if (!fetch && !read && inv) return false;
103    if (pkt->cmd == MemCmd::CleanEvict) return false;
104
105    if (onMiss) {
106        return !inCache(addr, is_secure) &&
107               !inMissQueue(addr, is_secure);
108    }
109
110    return true;
111}
112
113bool
114BasePrefetcher::inCache(Addr addr, bool is_secure) const
115{
116    if (cache->inCache(addr, is_secure)) {
117        return true;
118    }
119    return false;
120}
121
122bool
123BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
124{
125    if (cache->inMissQueue(addr, is_secure)) {
126        return true;
127    }
128    return false;
129}
130
131bool
132BasePrefetcher::samePage(Addr a, Addr b) const
133{
134    return roundDown(a, pageBytes) == roundDown(b, pageBytes);
135}
136
137Addr
138BasePrefetcher::blockAddress(Addr a) const
139{
140    return a & ~(blkSize-1);
141}
142
143Addr
144BasePrefetcher::blockIndex(Addr a) const
145{
146    return a >> lBlkSize;
147}
148
149Addr
150BasePrefetcher::pageAddress(Addr a) const
151{
152    return roundDown(a, pageBytes);
153}
154
155Addr
156BasePrefetcher::pageOffset(Addr a) const
157{
158    return a & (pageBytes - 1);
159}
160
161Addr
162BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
163{
164    return page + (blockIndex << lBlkSize);
165}
166