base.cc revision 10883:9294c4a60251 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include <list>
50
51#include "mem/cache/prefetch/base.hh"
52#include "mem/cache/base.hh"
53#include "sim/system.hh"
54
55BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
56    : ClockedObject(p), cache(nullptr), blkSize(0), system(p->sys),
57      onMiss(p->on_miss), onRead(p->on_read),
58      onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
59      masterId(system->getMasterId(name())),
60      pageBytes(system->getPageBytes())
61{
62}
63
64void
65BasePrefetcher::setCache(BaseCache *_cache)
66{
67    assert(!cache);
68    cache = _cache;
69    blkSize = cache->getBlockSize();
70}
71
72void
73BasePrefetcher::regStats()
74{
75    pfIssued
76        .name(name() + ".num_hwpf_issued")
77        .desc("number of hwpf issued")
78        ;
79}
80
81bool
82BasePrefetcher::observeAccess(const PacketPtr &pkt) const
83{
84    Addr addr = pkt->getAddr();
85    bool fetch = pkt->req->isInstFetch();
86    bool read = pkt->isRead();
87    bool inv = pkt->isInvalidate();
88    bool is_secure = pkt->isSecure();
89
90    if (pkt->req->isUncacheable()) return false;
91    if (fetch && !onInst) return false;
92    if (!fetch && !onData) return false;
93    if (!fetch && read && !onRead) return false;
94    if (!fetch && !read && !onWrite) return false;
95    if (!fetch && !read && inv) return false;
96    if (pkt->cmd == MemCmd::CleanEvict) return false;
97
98    if (onMiss) {
99        return !inCache(addr, is_secure) &&
100               !inMissQueue(addr, is_secure);
101    }
102
103    return true;
104}
105
106bool
107BasePrefetcher::inCache(Addr addr, bool is_secure) const
108{
109    if (cache->inCache(addr, is_secure)) {
110        return true;
111    }
112    return false;
113}
114
115bool
116BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
117{
118    if (cache->inMissQueue(addr, is_secure)) {
119        return true;
120    }
121    return false;
122}
123
124bool
125BasePrefetcher::samePage(Addr a, Addr b) const
126{
127    return roundDown(a, pageBytes) == roundDown(b, pageBytes);
128}
129
130
131