base.cc revision 8831
12810SN/A/* 22810SN/A * Copyright (c) 2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Ron Dreslinski 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Hardware Prefetcher Definition. 342810SN/A */ 352810SN/A 366658Snate@binkert.org#include <list> 376658Snate@binkert.org 385875Ssteve.reinhardt@amd.com#include "arch/isa_traits.hh" 392810SN/A#include "base/trace.hh" 406658Snate@binkert.org#include "config/the_isa.hh" 418232Snate@binkert.org#include "debug/HWPrefetch.hh" 428229Snate@binkert.org#include "mem/cache/prefetch/base.hh" 435338Sstever@gmail.com#include "mem/cache/base.hh" 442814SN/A#include "mem/request.hh" 452810SN/A 468831Smrinmoy.ghosh@arm.comBasePrefetcher::BasePrefetcher(const Params *p) 478831Smrinmoy.ghosh@arm.com : SimObject(p), size(p->size), latency(p->latency), degree(p->degree), 488831Smrinmoy.ghosh@arm.com useContextId(p->use_cpu_id), pageStop(!p->cross_pages), 498831Smrinmoy.ghosh@arm.com serialSquash(p->serial_squash), onlyData(p->data_accesses_only) 502810SN/A{ 512810SN/A} 522810SN/A 532810SN/Avoid 542810SN/ABasePrefetcher::setCache(BaseCache *_cache) 552810SN/A{ 562810SN/A cache = _cache; 572810SN/A blkSize = cache->getBlockSize(); 582810SN/A} 592810SN/A 602810SN/Avoid 618831Smrinmoy.ghosh@arm.comBasePrefetcher::regStats() 622810SN/A{ 632810SN/A pfIdentified 648831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_identified") 652810SN/A .desc("number of hwpf identified") 662810SN/A ; 672810SN/A 682810SN/A pfMSHRHit 698831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_mshr") 702810SN/A .desc("number of hwpf that were already in mshr") 712810SN/A ; 722810SN/A 732810SN/A pfCacheHit 748831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_cache") 752810SN/A .desc("number of hwpf that were already in the cache") 762810SN/A ; 772810SN/A 782810SN/A pfBufferHit 798831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher") 802810SN/A .desc("number of hwpf that were already in the prefetch queue") 812810SN/A ; 822810SN/A 832810SN/A pfRemovedFull 848831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_evicted") 852810SN/A .desc("number of hwpf removed due to no buffer left") 862810SN/A ; 872810SN/A 882810SN/A pfRemovedMSHR 898831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit") 902810SN/A .desc("number of hwpf removed because MSHR allocated") 912810SN/A ; 922810SN/A 932810SN/A pfIssued 948831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_issued") 952810SN/A .desc("number of hwpf issued") 962810SN/A ; 972810SN/A 982810SN/A pfSpanPage 998831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_span_page") 1002810SN/A .desc("number of hwpf spanning a virtual page") 1012810SN/A ; 1022810SN/A 1032810SN/A pfSquashed 1048831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_squashed_from_miss") 1055875Ssteve.reinhardt@amd.com .desc("number of hwpf that got squashed due to a miss " 1065875Ssteve.reinhardt@amd.com "aborting calculation time") 1072810SN/A ; 1082810SN/A} 1092810SN/A 1103861SN/Ainline bool 1113861SN/ABasePrefetcher::inCache(Addr addr) 1123861SN/A{ 1133861SN/A if (cache->inCache(addr)) { 1143861SN/A pfCacheHit++; 1153861SN/A return true; 1163861SN/A } 1173861SN/A return false; 1183861SN/A} 1193861SN/A 1203861SN/Ainline bool 1213861SN/ABasePrefetcher::inMissQueue(Addr addr) 1223861SN/A{ 1233861SN/A if (cache->inMissQueue(addr)) { 1243861SN/A pfMSHRHit++; 1253861SN/A return true; 1263861SN/A } 1273861SN/A return false; 1283861SN/A} 1293861SN/A 1303349SN/APacketPtr 1312810SN/ABasePrefetcher::getPacket() 1322810SN/A{ 1335875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Requesting a hw_pf to issue\n"); 1342810SN/A 1352810SN/A if (pf.empty()) { 1365875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "No HW_PF found\n"); 1372810SN/A return NULL; 1382810SN/A } 1392810SN/A 1408533SLisa.Hsu@amd.com PacketPtr pkt = *pf.begin(); 1418509SAli.Saidi@ARM.com while (!pf.empty()) { 1422810SN/A pkt = *pf.begin(); 1432810SN/A pf.pop_front(); 1445875Ssteve.reinhardt@amd.com 1458509SAli.Saidi@ARM.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 1468509SAli.Saidi@ARM.com 1478509SAli.Saidi@ARM.com if (!inCache(blk_addr) && !inMissQueue(blk_addr)) 1488509SAli.Saidi@ARM.com // we found a prefetch, return it 1498509SAli.Saidi@ARM.com break; 1508509SAli.Saidi@ARM.com 1518509SAli.Saidi@ARM.com DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n", pkt->getAddr()); 1528509SAli.Saidi@ARM.com delete pkt->req; 1538509SAli.Saidi@ARM.com delete pkt; 1545875Ssteve.reinhardt@amd.com 1552810SN/A if (pf.empty()) { 1564628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 1578509SAli.Saidi@ARM.com return NULL; // None left, all were in cache 1582810SN/A } 1598509SAli.Saidi@ARM.com } 1602810SN/A 1612810SN/A pfIssued++; 1625875Ssteve.reinhardt@amd.com assert(pkt != NULL); 1635875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr()); 1642810SN/A return pkt; 1652810SN/A} 1662810SN/A 1675875Ssteve.reinhardt@amd.com 1685875Ssteve.reinhardt@amd.comTick 1695875Ssteve.reinhardt@amd.comBasePrefetcher::notify(PacketPtr &pkt, Tick time) 1702810SN/A{ 1716105Ssteve.reinhardt@amd.com if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) { 1725875Ssteve.reinhardt@amd.com // Calculate the blk address 1735875Ssteve.reinhardt@amd.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 1742810SN/A 1755875Ssteve.reinhardt@amd.com // Check if miss is in pfq, if so remove it 1765875Ssteve.reinhardt@amd.com std::list<PacketPtr>::iterator iter = inPrefetch(blk_addr); 1772810SN/A if (iter != pf.end()) { 1785875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: " 1795875Ssteve.reinhardt@amd.com "0x%x, removing it\n", blk_addr); 1802810SN/A pfRemovedMSHR++; 1815875Ssteve.reinhardt@amd.com delete (*iter)->req; 1825875Ssteve.reinhardt@amd.com delete (*iter); 1832810SN/A pf.erase(iter); 1842810SN/A if (pf.empty()) 1854628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 1862810SN/A } 1872810SN/A 1885875Ssteve.reinhardt@amd.com // Remove anything in queue with delay older than time 1895875Ssteve.reinhardt@amd.com // since everything is inserted in time order, start from end 1905875Ssteve.reinhardt@amd.com // and work until pf.empty() or time is earlier 1915875Ssteve.reinhardt@amd.com // This is done to emulate Aborting the previous work on a new miss 1925875Ssteve.reinhardt@amd.com // Needed for serial calculators like GHB 1932810SN/A if (serialSquash) { 1942810SN/A iter = pf.end(); 1952810SN/A iter--; 1962810SN/A while (!pf.empty() && ((*iter)->time >= time)) { 1972810SN/A pfSquashed++; 1985875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n", 1995875Ssteve.reinhardt@amd.com (*iter)->getAddr()); 2005875Ssteve.reinhardt@amd.com delete (*iter)->req; 2015875Ssteve.reinhardt@amd.com delete (*iter); 2025875Ssteve.reinhardt@amd.com pf.erase(iter); 2032810SN/A iter--; 2042810SN/A } 2052810SN/A if (pf.empty()) 2064628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 2072810SN/A } 2082810SN/A 2092810SN/A 2102810SN/A std::list<Addr> addresses; 2112810SN/A std::list<Tick> delays; 2122810SN/A calculatePrefetch(pkt, addresses, delays); 2132810SN/A 2145875Ssteve.reinhardt@amd.com std::list<Addr>::iterator addrIter = addresses.begin(); 2155875Ssteve.reinhardt@amd.com std::list<Tick>::iterator delayIter = delays.begin(); 2165875Ssteve.reinhardt@amd.com for (; addrIter != addresses.end(); ++addrIter, ++delayIter) { 2175875Ssteve.reinhardt@amd.com Addr addr = *addrIter; 2185875Ssteve.reinhardt@amd.com 2192810SN/A pfIdentified++; 2205875Ssteve.reinhardt@amd.com 2215875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Found a pf candidate addr: 0x%x, " 2225875Ssteve.reinhardt@amd.com "inserting into prefetch queue with delay %d time %d\n", 2235875Ssteve.reinhardt@amd.com addr, *delayIter, time); 2245875Ssteve.reinhardt@amd.com 2255875Ssteve.reinhardt@amd.com // Check if it is already in the pf buffer 2265875Ssteve.reinhardt@amd.com if (inPrefetch(addr) != pf.end()) { 2275875Ssteve.reinhardt@amd.com pfBufferHit++; 2285875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n"); 2295875Ssteve.reinhardt@amd.com continue; 2305875Ssteve.reinhardt@amd.com } 2315875Ssteve.reinhardt@amd.com 2325875Ssteve.reinhardt@amd.com // create a prefetch memreq 2335875Ssteve.reinhardt@amd.com Request *prefetchReq = new Request(*addrIter, blkSize, 0); 2345875Ssteve.reinhardt@amd.com PacketPtr prefetch = 2355875Ssteve.reinhardt@amd.com new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast); 2362825SN/A prefetch->allocate(); 2375714Shsul@eecs.umich.edu prefetch->req->setThreadContext(pkt->req->contextId(), 2385714Shsul@eecs.umich.edu pkt->req->threadId()); 2392814SN/A 2405875Ssteve.reinhardt@amd.com prefetch->time = time + (*delayIter); // @todo ADD LATENCY HERE 2412810SN/A 2425875Ssteve.reinhardt@amd.com // We just remove the head if we are full 2435875Ssteve.reinhardt@amd.com if (pf.size() == size) { 2442810SN/A pfRemovedFull++; 2455875Ssteve.reinhardt@amd.com PacketPtr old_pkt = *pf.begin(); 2465875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Prefetch queue full, " 2475875Ssteve.reinhardt@amd.com "removing oldest 0x%x\n", old_pkt->getAddr()); 2485875Ssteve.reinhardt@amd.com delete old_pkt->req; 2495875Ssteve.reinhardt@amd.com delete old_pkt; 2502810SN/A pf.pop_front(); 2512810SN/A } 2522810SN/A 2532810SN/A pf.push_back(prefetch); 2542810SN/A } 2552810SN/A } 2565875Ssteve.reinhardt@amd.com 2575875Ssteve.reinhardt@amd.com return pf.empty() ? 0 : pf.front()->time; 2582810SN/A} 2592810SN/A 2603349SN/Astd::list<PacketPtr>::iterator 2612810SN/ABasePrefetcher::inPrefetch(Addr address) 2622810SN/A{ 2635875Ssteve.reinhardt@amd.com // Guaranteed to only be one match, we always check before inserting 2643349SN/A std::list<PacketPtr>::iterator iter; 2655875Ssteve.reinhardt@amd.com for (iter = pf.begin(); iter != pf.end(); iter++) { 2662814SN/A if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) { 2672810SN/A return iter; 2682810SN/A } 2692810SN/A } 2702810SN/A return pf.end(); 2712810SN/A} 2722810SN/A 2735875Ssteve.reinhardt@amd.combool 2745875Ssteve.reinhardt@amd.comBasePrefetcher::samePage(Addr a, Addr b) 2755875Ssteve.reinhardt@amd.com{ 2765875Ssteve.reinhardt@amd.com return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize); 2775875Ssteve.reinhardt@amd.com} 2788831Smrinmoy.ghosh@arm.com 2798831Smrinmoy.ghosh@arm.com 280