base.cc revision 10714
12810SN/A/*
210623Smitch.hayenga@arm.com * Copyright (c) 2013-2014 ARM Limited
39546Sandreas.hansson@arm.com * All rights reserved.
49546Sandreas.hansson@arm.com *
59546Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
69546Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
79546Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
89546Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
99546Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
109546Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
119546Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
129546Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
139546Sandreas.hansson@arm.com *
142810SN/A * Copyright (c) 2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Ron Dreslinski
4110623Smitch.hayenga@arm.com *          Mitch Hayenga
422810SN/A */
432810SN/A
442810SN/A/**
452810SN/A * @file
462810SN/A * Hardware Prefetcher Definition.
472810SN/A */
482810SN/A
496658Snate@binkert.org#include <list>
506658Snate@binkert.org
518229Snate@binkert.org#include "mem/cache/prefetch/base.hh"
525338Sstever@gmail.com#include "mem/cache/base.hh"
538832SAli.Saidi@ARM.com#include "sim/system.hh"
542810SN/A
5510623Smitch.hayenga@arm.comBasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
5610623Smitch.hayenga@arm.com    : ClockedObject(p), cache(nullptr), blkSize(0), system(p->sys),
5710623Smitch.hayenga@arm.com      onMiss(p->on_miss), onRead(p->on_read),
5810623Smitch.hayenga@arm.com      onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
5910466Sandreas.hansson@arm.com      masterId(system->getMasterId(name())),
6010466Sandreas.hansson@arm.com      pageBytes(system->getPageBytes())
612810SN/A{
622810SN/A}
632810SN/A
642810SN/Avoid
652810SN/ABasePrefetcher::setCache(BaseCache *_cache)
662810SN/A{
6710360Sandreas.hansson@arm.com    assert(!cache);
682810SN/A    cache = _cache;
692810SN/A    blkSize = cache->getBlockSize();
702810SN/A}
712810SN/A
722810SN/Avoid
738831Smrinmoy.ghosh@arm.comBasePrefetcher::regStats()
742810SN/A{
752810SN/A    pfIssued
7610623Smitch.hayenga@arm.com        .name(name() + ".num_hwpf_issued")
772810SN/A        .desc("number of hwpf issued")
782810SN/A        ;
792810SN/A}
802810SN/A
8110623Smitch.hayenga@arm.combool
8210623Smitch.hayenga@arm.comBasePrefetcher::observeAccess(const PacketPtr &pkt) const
8310623Smitch.hayenga@arm.com{
8410623Smitch.hayenga@arm.com    Addr addr = pkt->getAddr();
8510623Smitch.hayenga@arm.com    bool fetch = pkt->req->isInstFetch();
8610626SCurtis.Dunham@arm.com    bool read = pkt->isRead();
8710626SCurtis.Dunham@arm.com    bool inv = pkt->isInvalidate();
8810623Smitch.hayenga@arm.com    bool is_secure = pkt->isSecure();
8910623Smitch.hayenga@arm.com
9010623Smitch.hayenga@arm.com    if (pkt->req->isUncacheable()) return false;
9110623Smitch.hayenga@arm.com    if (fetch && !onInst) return false;
9210623Smitch.hayenga@arm.com    if (!fetch && !onData) return false;
9310623Smitch.hayenga@arm.com    if (!fetch && read && !onRead) return false;
9410623Smitch.hayenga@arm.com    if (!fetch && !read && !onWrite) return false;
9510626SCurtis.Dunham@arm.com    if (!fetch && !read && inv) return false;
9610623Smitch.hayenga@arm.com
9710623Smitch.hayenga@arm.com    if (onMiss) {
9810623Smitch.hayenga@arm.com        return !inCache(addr, is_secure) &&
9910623Smitch.hayenga@arm.com               !inMissQueue(addr, is_secure);
10010623Smitch.hayenga@arm.com    }
10110623Smitch.hayenga@arm.com
10210623Smitch.hayenga@arm.com    return true;
10310623Smitch.hayenga@arm.com}
10410623Smitch.hayenga@arm.com
10510623Smitch.hayenga@arm.combool
10610623Smitch.hayenga@arm.comBasePrefetcher::inCache(Addr addr, bool is_secure) const
1073861SN/A{
10810028SGiacomo.Gabrielli@arm.com    if (cache->inCache(addr, is_secure)) {
1093861SN/A        return true;
1103861SN/A    }
1113861SN/A    return false;
1123861SN/A}
1133861SN/A
11410623Smitch.hayenga@arm.combool
11510623Smitch.hayenga@arm.comBasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
1163861SN/A{
11710028SGiacomo.Gabrielli@arm.com    if (cache->inMissQueue(addr, is_secure)) {
1183861SN/A        return true;
1193861SN/A    }
1203861SN/A    return false;
1213861SN/A}
1223861SN/A
1235875Ssteve.reinhardt@amd.combool
12410466Sandreas.hansson@arm.comBasePrefetcher::samePage(Addr a, Addr b) const
1255875Ssteve.reinhardt@amd.com{
12610466Sandreas.hansson@arm.com    return roundDown(a, pageBytes) == roundDown(b, pageBytes);
1275875Ssteve.reinhardt@amd.com}
1288831Smrinmoy.ghosh@arm.com
1298831Smrinmoy.ghosh@arm.com
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