Prefetcher.py revision 10382:452a5f178ec5 
1# Copyright (c) 2012 ARM Limited
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13# Copyright (c) 2005 The Regents of The University of Michigan
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39# Authors: Ron Dreslinski
40
41from ClockedObject import ClockedObject
42from m5.params import *
43from m5.proxy import *
44
45class BasePrefetcher(ClockedObject):
46    type = 'BasePrefetcher'
47    abstract = True
48    cxx_header = "mem/cache/prefetch/base.hh"
49    size = Param.Int(100,
50         "Number of entries in the hardware prefetch queue")
51    cross_pages = Param.Bool(False,
52         "Allow prefetches to cross virtual page boundaries")
53    serial_squash = Param.Bool(False,
54         "Squash prefetches with a later time on a subsequent miss")
55    degree = Param.Int(1,
56         "Degree of the prefetch depth")
57    latency = Param.Cycles('1', "Latency of the prefetcher")
58    use_master_id = Param.Bool(True,
59         "Use the master id to separate calculations of prefetches")
60    data_accesses_only = Param.Bool(False,
61         "Only prefetch on data not on instruction accesses")
62    on_miss_only = Param.Bool(False,
63         "Only prefetch on miss (as opposed to always)")
64    on_read_only = Param.Bool(False,
65         "Only prefetch on read requests (write requests ignored)")
66    on_prefetch = Param.Bool(True,
67         "Let lower cache prefetcher train on prefetch requests")
68    inst_tagged = Param.Bool(True,
69         "Perform a tagged prefetch for instruction fetches always")
70    sys = Param.System(Parent.any, "System this device belongs to")
71
72class StridePrefetcher(BasePrefetcher):
73    type = 'StridePrefetcher'
74    cxx_class = 'StridePrefetcher'
75    cxx_header = "mem/cache/prefetch/stride.hh"
76
77class TaggedPrefetcher(BasePrefetcher):
78    type = 'TaggedPrefetcher'
79    cxx_class = 'TaggedPrefetcher'
80    cxx_header = "mem/cache/prefetch/tagged.hh"
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