Prefetcher.py revision 9288
19288Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited
29288Sandreas.hansson@arm.com# All rights reserved.
39288Sandreas.hansson@arm.com#
49288Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
59288Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
69288Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
79288Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
89288Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
99288Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
109288Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
119288Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
129288Sandreas.hansson@arm.com#
139288Sandreas.hansson@arm.com# Copyright (c) 2005 The Regents of The University of Michigan
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179288Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
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249288Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from
259288Sandreas.hansson@arm.com# this software without specific prior written permission.
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279288Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
289288Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
299288Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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369288Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
379288Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
389288Sandreas.hansson@arm.com#
399288Sandreas.hansson@arm.com# Authors: Ron Dreslinski
409288Sandreas.hansson@arm.com
419288Sandreas.hansson@arm.comfrom ClockedObject import ClockedObject
428831Smrinmoy.ghosh@arm.comfrom m5.params import *
438832SAli.Saidi@ARM.comfrom m5.proxy import *
448832SAli.Saidi@ARM.com
459288Sandreas.hansson@arm.comclass BasePrefetcher(ClockedObject):
468831Smrinmoy.ghosh@arm.com    type = 'BasePrefetcher'
478831Smrinmoy.ghosh@arm.com    abstract = True
488831Smrinmoy.ghosh@arm.com    size = Param.Int(100,
498831Smrinmoy.ghosh@arm.com         "Number of entries in the hardware prefetch queue")
508831Smrinmoy.ghosh@arm.com    cross_pages = Param.Bool(False,
518831Smrinmoy.ghosh@arm.com         "Allow prefetches to cross virtual page boundaries")
528831Smrinmoy.ghosh@arm.com    serial_squash = Param.Bool(False,
538831Smrinmoy.ghosh@arm.com         "Squash prefetches with a later time on a subsequent miss")
548831Smrinmoy.ghosh@arm.com    degree = Param.Int(1,
558831Smrinmoy.ghosh@arm.com         "Degree of the prefetch depth")
569288Sandreas.hansson@arm.com    latency = Param.Cycles('1', "Latency of the prefetcher")
578832SAli.Saidi@ARM.com    use_master_id = Param.Bool(True,
588832SAli.Saidi@ARM.com         "Use the master id to separate calculations of prefetches")
598831Smrinmoy.ghosh@arm.com    data_accesses_only = Param.Bool(False,
608831Smrinmoy.ghosh@arm.com         "Only prefetch on data not on instruction accesses")
618832SAli.Saidi@ARM.com    sys = Param.System(Parent.any, "System this device belongs to")
628831Smrinmoy.ghosh@arm.com
638831Smrinmoy.ghosh@arm.comclass GHBPrefetcher(BasePrefetcher):
648831Smrinmoy.ghosh@arm.com    type = 'GHBPrefetcher'
658831Smrinmoy.ghosh@arm.com    cxx_class = 'GHBPrefetcher'
668831Smrinmoy.ghosh@arm.com
678831Smrinmoy.ghosh@arm.comclass StridePrefetcher(BasePrefetcher):
688831Smrinmoy.ghosh@arm.com    type = 'StridePrefetcher'
698831Smrinmoy.ghosh@arm.com    cxx_class = 'StridePrefetcher'
708831Smrinmoy.ghosh@arm.com
718831Smrinmoy.ghosh@arm.comclass TaggedPrefetcher(BasePrefetcher):
728831Smrinmoy.ghosh@arm.com    type = 'TaggedPrefetcher'
738831Smrinmoy.ghosh@arm.com    cxx_class = 'TaggedPrefetcher'
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