Prefetcher.py revision 13665
17405SAli.Saidi@ARM.com# Copyright (c) 2012, 2014 ARM Limited
211573SDylan.Johnson@ARM.com# All rights reserved.
37405SAli.Saidi@ARM.com#
47405SAli.Saidi@ARM.com# The license below extends only to copyright in the software and shall
57405SAli.Saidi@ARM.com# not be construed as granting a license to any other intellectual
67405SAli.Saidi@ARM.com# property including but not limited to intellectual property relating
77405SAli.Saidi@ARM.com# to a hardware implementation of the functionality of the software
87405SAli.Saidi@ARM.com# licensed hereunder.  You may use the software subject to the license
97405SAli.Saidi@ARM.com# terms below provided that you ensure that this notice is replicated
107405SAli.Saidi@ARM.com# unmodified and in its entirety in all distributions of the software,
117405SAli.Saidi@ARM.com# modified or unmodified, in source code or in binary form.
127405SAli.Saidi@ARM.com#
137405SAli.Saidi@ARM.com# Copyright (c) 2005 The Regents of The University of Michigan
147405SAli.Saidi@ARM.com# All rights reserved.
157405SAli.Saidi@ARM.com#
167405SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without
177405SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are
187405SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright
197405SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer;
207405SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright
217405SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the
227405SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution;
237405SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its
247405SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from
257405SAli.Saidi@ARM.com# this software without specific prior written permission.
267405SAli.Saidi@ARM.com#
277405SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
287405SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
297405SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
307405SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
317405SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
327405SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
337405SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
347405SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
357405SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
367405SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
377405SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
387405SAli.Saidi@ARM.com#
397405SAli.Saidi@ARM.com# Authors: Ron Dreslinski
407405SAli.Saidi@ARM.com#          Mitch Hayenga
417405SAli.Saidi@ARM.com
4211793Sbrandon.potter@amd.comfrom m5.SimObject import *
4310461SAndreas.Sandberg@ARM.comfrom m5.params import *
449050Schander.sudanthi@arm.comfrom m5.proxy import *
4511793Sbrandon.potter@amd.com
468887Sgeoffrey.blake@arm.comfrom m5.objects.ClockedObject import ClockedObject
478232Snate@binkert.orgfrom m5.objects.IndexingPolicies import *
488232Snate@binkert.orgfrom m5.objects.ReplacementPolicies import *
4910844Sandreas.sandberg@arm.com
509384SAndreas.Sandberg@arm.comclass HWPProbeEvent(object):
517678Sgblack@eecs.umich.edu    def __init__(self, prefetcher, obj, *listOfNames):
528059SAli.Saidi@ARM.com        self.obj = obj
538284SAli.Saidi@ARM.com        self.prefetcher = prefetcher
547405SAli.Saidi@ARM.com        self.names = listOfNames
557405SAli.Saidi@ARM.com
567405SAli.Saidi@ARM.com    def register(self):
577405SAli.Saidi@ARM.com        if self.obj:
5810037SARM gem5 Developers            for name in self.names:
5910037SARM gem5 Developers                self.prefetcher.getCCObject().addEventProbe(
6011768SCurtis.Dunham@arm.com                    self.obj.getCCObject(), name)
6110037SARM gem5 Developers
6210037SARM gem5 Developersclass BasePrefetcher(ClockedObject):
6310037SARM gem5 Developers    type = 'BasePrefetcher'
6410037SARM gem5 Developers    abstract = True
6511768SCurtis.Dunham@arm.com    cxx_header = "mem/cache/prefetch/base.hh"
6610037SARM gem5 Developers    cxx_exports = [
6710037SARM gem5 Developers        PyBindMethod("addEventProbe"),
6811768SCurtis.Dunham@arm.com    ]
6911768SCurtis.Dunham@arm.com    sys = Param.System(Parent.any, "System this prefetcher belongs to")
7011768SCurtis.Dunham@arm.com
7111768SCurtis.Dunham@arm.com    # Get the block size from the parent (system)
7211768SCurtis.Dunham@arm.com    block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
7311768SCurtis.Dunham@arm.com
7411768SCurtis.Dunham@arm.com    on_miss = Param.Bool(False, "Only notify prefetcher on misses")
7511768SCurtis.Dunham@arm.com    on_read = Param.Bool(True, "Notify prefetcher on reads")
7611768SCurtis.Dunham@arm.com    on_write = Param.Bool(True, "Notify prefetcher on writes")
7711768SCurtis.Dunham@arm.com    on_data  = Param.Bool(True, "Notify prefetcher on data accesses")
7811768SCurtis.Dunham@arm.com    on_inst  = Param.Bool(True, "Notify prefetcher on instruction accesses")
7911768SCurtis.Dunham@arm.com    prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
8010037SARM gem5 Developers        "Notify the hardware prefetcher on every access (not just misses)")
8110037SARM gem5 Developers    use_virtual_addresses = Param.Bool(False,
8210037SARM gem5 Developers        "Use virtual addresses for prefetching")
8311768SCurtis.Dunham@arm.com
8411768SCurtis.Dunham@arm.com    _events = []
8511768SCurtis.Dunham@arm.com    def addEvent(self, newObject):
8611768SCurtis.Dunham@arm.com        self._events.append(newObject)
8711768SCurtis.Dunham@arm.com
8811768SCurtis.Dunham@arm.com    # Override the normal SimObject::regProbeListeners method and
8911768SCurtis.Dunham@arm.com    # register deferred event handlers.
9011768SCurtis.Dunham@arm.com    def regProbeListeners(self):
9110037SARM gem5 Developers        for event in self._events:
9211768SCurtis.Dunham@arm.com           event.register()
9311768SCurtis.Dunham@arm.com        self.getCCObject().regProbeListeners()
9411768SCurtis.Dunham@arm.com
9511768SCurtis.Dunham@arm.com    def listenFromProbe(self, simObj, *probeNames):
9610037SARM gem5 Developers        if not isinstance(simObj, SimObject):
9711768SCurtis.Dunham@arm.com            raise TypeError("argument must be of SimObject type")
9811768SCurtis.Dunham@arm.com        if len(probeNames) <= 0:
9911768SCurtis.Dunham@arm.com            raise TypeError("probeNames must have at least one element")
10011768SCurtis.Dunham@arm.com        self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
10111768SCurtis.Dunham@arm.com
10211768SCurtis.Dunham@arm.comclass QueuedPrefetcher(BasePrefetcher):
10311768SCurtis.Dunham@arm.com    type = "QueuedPrefetcher"
10411768SCurtis.Dunham@arm.com    abstract = True
10511768SCurtis.Dunham@arm.com    cxx_class = "QueuedPrefetcher"
10611768SCurtis.Dunham@arm.com    cxx_header = "mem/cache/prefetch/queued.hh"
10711768SCurtis.Dunham@arm.com    latency = Param.Int(1, "Latency for generated prefetches")
10811768SCurtis.Dunham@arm.com    queue_size = Param.Int(32, "Maximum number of queued prefetches")
10911768SCurtis.Dunham@arm.com    queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
11011768SCurtis.Dunham@arm.com    queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
11111768SCurtis.Dunham@arm.com    cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
11211768SCurtis.Dunham@arm.com
11311768SCurtis.Dunham@arm.com    tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
11411768SCurtis.Dunham@arm.com
11510037SARM gem5 Developersclass StridePrefetcher(QueuedPrefetcher):
11611768SCurtis.Dunham@arm.com    type = 'StridePrefetcher'
11711768SCurtis.Dunham@arm.com    cxx_class = 'StridePrefetcher'
11811768SCurtis.Dunham@arm.com    cxx_header = "mem/cache/prefetch/stride.hh"
11911768SCurtis.Dunham@arm.com
12010037SARM gem5 Developers    # Do not consult stride prefetcher on instruction accesses
12111768SCurtis.Dunham@arm.com    on_inst = False
12211768SCurtis.Dunham@arm.com
12311768SCurtis.Dunham@arm.com    max_conf = Param.Int(7, "Maximum confidence level")
12411768SCurtis.Dunham@arm.com    thresh_conf = Param.Int(4, "Threshold confidence level")
12511768SCurtis.Dunham@arm.com    min_conf = Param.Int(0, "Minimum confidence level")
12611768SCurtis.Dunham@arm.com    start_conf = Param.Int(4, "Starting confidence for new entries")
12710037SARM gem5 Developers
12811768SCurtis.Dunham@arm.com    table_sets = Param.Int(16, "Number of sets in PC lookup table")
12911768SCurtis.Dunham@arm.com    table_assoc = Param.Int(4, "Associativity of PC lookup table")
13011768SCurtis.Dunham@arm.com    use_master_id = Param.Bool(True, "Use master id based history")
13111768SCurtis.Dunham@arm.com
13211768SCurtis.Dunham@arm.com    degree = Param.Int(4, "Number of prefetches to generate")
13311768SCurtis.Dunham@arm.com
13411768SCurtis.Dunham@arm.com    # Get replacement policy
13511768SCurtis.Dunham@arm.com    replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
13611768SCurtis.Dunham@arm.com        "Replacement policy")
13711768SCurtis.Dunham@arm.com
13811768SCurtis.Dunham@arm.comclass TaggedPrefetcher(QueuedPrefetcher):
13911768SCurtis.Dunham@arm.com    type = 'TaggedPrefetcher'
14011768SCurtis.Dunham@arm.com    cxx_class = 'TaggedPrefetcher'
14111768SCurtis.Dunham@arm.com    cxx_header = "mem/cache/prefetch/tagged.hh"
14211768SCurtis.Dunham@arm.com
14311768SCurtis.Dunham@arm.com    degree = Param.Int(2, "Number of prefetches to generate")
14411768SCurtis.Dunham@arm.com
14511768SCurtis.Dunham@arm.comclass SignaturePathPrefetcher(QueuedPrefetcher):
14611768SCurtis.Dunham@arm.com    type = 'SignaturePathPrefetcher'
14711768SCurtis.Dunham@arm.com    cxx_class = 'SignaturePathPrefetcher'
14811768SCurtis.Dunham@arm.com    cxx_header = "mem/cache/prefetch/signature_path.hh"
14911768SCurtis.Dunham@arm.com
15011768SCurtis.Dunham@arm.com    signature_shift = Param.UInt8(3,
15111768SCurtis.Dunham@arm.com        "Number of bits to shift when calculating a new signature");
15211768SCurtis.Dunham@arm.com    signature_bits = Param.UInt16(12,
15311768SCurtis.Dunham@arm.com        "Size of the signature, in bits");
15411768SCurtis.Dunham@arm.com    signature_table_entries = Param.MemorySize("1024",
15511768SCurtis.Dunham@arm.com        "Number of entries of the signature table")
15611768SCurtis.Dunham@arm.com    signature_table_assoc = Param.Unsigned(2,
15711768SCurtis.Dunham@arm.com        "Associativity of the signature table")
15811768SCurtis.Dunham@arm.com    signature_table_indexing_policy = Param.BaseIndexingPolicy(
15911768SCurtis.Dunham@arm.com        SetAssociative(entry_size = 1, assoc = Parent.signature_table_assoc,
16011768SCurtis.Dunham@arm.com        size = Parent.signature_table_entries),
16111768SCurtis.Dunham@arm.com        "Indexing policy of the signature table")
16211768SCurtis.Dunham@arm.com    signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
16311768SCurtis.Dunham@arm.com        "Replacement policy of the signature table")
16411768SCurtis.Dunham@arm.com
16511768SCurtis.Dunham@arm.com    max_counter_value = Param.UInt8(7, "Maximum pattern counter value")
16611768SCurtis.Dunham@arm.com    pattern_table_entries = Param.MemorySize("4096",
16711768SCurtis.Dunham@arm.com        "Number of entries of the pattern table")
16811768SCurtis.Dunham@arm.com    pattern_table_assoc = Param.Unsigned(1,
16911768SCurtis.Dunham@arm.com        "Associativity of the pattern table")
17011768SCurtis.Dunham@arm.com    strides_per_pattern_entry = Param.Unsigned(4,
17111768SCurtis.Dunham@arm.com        "Number of strides stored in each pattern entry")
17211768SCurtis.Dunham@arm.com    pattern_table_indexing_policy = Param.BaseIndexingPolicy(
17311768SCurtis.Dunham@arm.com        SetAssociative(entry_size = 1, assoc = Parent.pattern_table_assoc,
17411768SCurtis.Dunham@arm.com        size = Parent.pattern_table_entries),
17511768SCurtis.Dunham@arm.com        "Indexing policy of the pattern table")
17611768SCurtis.Dunham@arm.com    pattern_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
17711768SCurtis.Dunham@arm.com        "Replacement policy of the pattern table")
17811768SCurtis.Dunham@arm.com
17911768SCurtis.Dunham@arm.com    prefetch_confidence_threshold = Param.Float(0.5,
18011768SCurtis.Dunham@arm.com        "Minimum confidence to issue prefetches")
18111768SCurtis.Dunham@arm.com    lookahead_confidence_threshold = Param.Float(0.75,
18211768SCurtis.Dunham@arm.com        "Minimum confidence to continue exploring lookahead entries")
18311768SCurtis.Dunham@arm.com
18411768SCurtis.Dunham@arm.comclass SignaturePathPrefetcherV2(SignaturePathPrefetcher):
18511768SCurtis.Dunham@arm.com    type = 'SignaturePathPrefetcherV2'
18611768SCurtis.Dunham@arm.com    cxx_class = 'SignaturePathPrefetcherV2'
18711768SCurtis.Dunham@arm.com    cxx_header = "mem/cache/prefetch/signature_path_v2.hh"
18811768SCurtis.Dunham@arm.com
18911768SCurtis.Dunham@arm.com    signature_table_entries = "256"
19011768SCurtis.Dunham@arm.com    signature_table_assoc = 1
19111768SCurtis.Dunham@arm.com    pattern_table_entries = "512"
19211768SCurtis.Dunham@arm.com    pattern_table_assoc = 1
19311768SCurtis.Dunham@arm.com    max_counter_value = 15
19411768SCurtis.Dunham@arm.com    prefetch_confidence_threshold = 0.25
19511768SCurtis.Dunham@arm.com    lookahead_confidence_threshold = 0.25
19611768SCurtis.Dunham@arm.com
19711768SCurtis.Dunham@arm.com    global_history_register_entries = Param.MemorySize("8",
19811768SCurtis.Dunham@arm.com        "Number of entries of global history register")
19911768SCurtis.Dunham@arm.com    global_history_register_indexing_policy = Param.BaseIndexingPolicy(
20011768SCurtis.Dunham@arm.com        SetAssociative(entry_size = 1,
20111768SCurtis.Dunham@arm.com        assoc = Parent.global_history_register_entries,
20211768SCurtis.Dunham@arm.com        size = Parent.global_history_register_entries),
20311768SCurtis.Dunham@arm.com        "Indexing policy of the global history register")
20411768SCurtis.Dunham@arm.com    global_history_register_replacement_policy = Param.BaseReplacementPolicy(
20510037SARM gem5 Developers        LRURP(), "Replacement policy of the global history register")
20610037SARM gem5 Developers
20710037SARM gem5 Developersclass AccessMapPatternMatchingPrefetcher(QueuedPrefetcher):
2089384SAndreas.Sandberg@arm.com    type = 'AccessMapPatternMatchingPrefetcher'
20910461SAndreas.Sandberg@ARM.com    cxx_class = 'AccessMapPatternMatchingPrefetcher'
21010461SAndreas.Sandberg@ARM.com    cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
21111165SRekai.GonzalezAlberquilla@arm.com
21210461SAndreas.Sandberg@ARM.com    start_degree = Param.Unsigned(4,
21310461SAndreas.Sandberg@ARM.com        "Initial degree (Maximum number of prefetches generated")
2149384SAndreas.Sandberg@arm.com    hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone")
21511770SCurtis.Dunham@arm.com    access_map_table_entries = Param.MemorySize("256",
21610037SARM gem5 Developers        "Number of entries in the access map table")
21710461SAndreas.Sandberg@ARM.com    access_map_table_assoc = Param.Unsigned(8,
21810461SAndreas.Sandberg@ARM.com        "Associativity of the access map table")
21910461SAndreas.Sandberg@ARM.com    access_map_table_indexing_policy = Param.BaseIndexingPolicy(
22010461SAndreas.Sandberg@ARM.com        SetAssociative(entry_size = 1, assoc = Parent.access_map_table_assoc,
22110461SAndreas.Sandberg@ARM.com        size = Parent.access_map_table_entries),
22210461SAndreas.Sandberg@ARM.com        "Indexing policy of the access map table")
22310609Sandreas.sandberg@arm.com    access_map_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
22410609Sandreas.sandberg@arm.com        "Replacement policy of the access map table")
22510609Sandreas.sandberg@arm.com    high_coverage_threshold = Param.Float(0.25,
22610037SARM gem5 Developers        "A prefetch coverage factor bigger than this is considered high")
22710037SARM gem5 Developers    low_coverage_threshold = Param.Float(0.125,
22810037SARM gem5 Developers        "A prefetch coverage factor smaller than this is considered low")
22910037SARM gem5 Developers    high_accuracy_threshold = Param.Float(0.5,
23011771SCurtis.Dunham@arm.com        "A prefetch accuracy factor bigger than this is considered high")
23110037SARM gem5 Developers    low_accuracy_threshold = Param.Float(0.25,
23210037SARM gem5 Developers        "A prefetch accuracy factor smaller than this is considered low")
23310037SARM gem5 Developers    high_cache_hit_threshold = Param.Float(0.875,
23410037SARM gem5 Developers        "A cache hit ratio bigger than this is considered high")
23510037SARM gem5 Developers    low_cache_hit_threshold = Param.Float(0.75,
23610037SARM gem5 Developers        "A cache hit ratio smaller than this is considered low")
23711771SCurtis.Dunham@arm.com    epoch_cycles = Param.Cycles(256000, "Cycles in an epoch period")
23810037SARM gem5 Developers    offchip_memory_latency = Param.Latency("30ns",
23910037SARM gem5 Developers        "Memory latency used to compute the required memory bandwidth")
24010037SARM gem5 Developers