Prefetcher.py revision 13427
110623Smitch.hayenga@arm.com# Copyright (c) 2012, 2014 ARM Limited 29288Sandreas.hansson@arm.com# All rights reserved. 39288Sandreas.hansson@arm.com# 49288Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 59288Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 69288Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 79288Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 89288Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 99288Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 109288Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 119288Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 129288Sandreas.hansson@arm.com# 139288Sandreas.hansson@arm.com# Copyright (c) 2005 The Regents of The University of Michigan 149288Sandreas.hansson@arm.com# All rights reserved. 159288Sandreas.hansson@arm.com# 169288Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 179288Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 189288Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 199288Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 209288Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 219288Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 229288Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 239288Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 249288Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 259288Sandreas.hansson@arm.com# this software without specific prior written permission. 269288Sandreas.hansson@arm.com# 279288Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289288Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299288Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309288Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319288Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329288Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339288Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349288Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359288Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369288Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379288Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389288Sandreas.hansson@arm.com# 399288Sandreas.hansson@arm.com# Authors: Ron Dreslinski 4010623Smitch.hayenga@arm.com# Mitch Hayenga 419288Sandreas.hansson@arm.com 429288Sandreas.hansson@arm.comfrom ClockedObject import ClockedObject 4313416Sjavier.bueno@metempsy.comfrom m5.SimObject import * 448831Smrinmoy.ghosh@arm.comfrom m5.params import * 458832SAli.Saidi@ARM.comfrom m5.proxy import * 4613427Sodanrc@yahoo.com.brfrom ReplacementPolicies import * 478832SAli.Saidi@ARM.com 4813416Sjavier.bueno@metempsy.comclass HWPProbeEvent(object): 4913416Sjavier.bueno@metempsy.com def __init__(self, prefetcher, obj, *listOfNames): 5013416Sjavier.bueno@metempsy.com self.obj = obj 5113416Sjavier.bueno@metempsy.com self.prefetcher = prefetcher 5213416Sjavier.bueno@metempsy.com self.names = listOfNames 5313416Sjavier.bueno@metempsy.com 5413416Sjavier.bueno@metempsy.com def register(self): 5513416Sjavier.bueno@metempsy.com if self.obj: 5613416Sjavier.bueno@metempsy.com for name in self.names: 5713416Sjavier.bueno@metempsy.com self.prefetcher.getCCObject().addEventProbe( 5813416Sjavier.bueno@metempsy.com self.obj.getCCObject(), name) 5913416Sjavier.bueno@metempsy.com 609288Sandreas.hansson@arm.comclass BasePrefetcher(ClockedObject): 618831Smrinmoy.ghosh@arm.com type = 'BasePrefetcher' 628831Smrinmoy.ghosh@arm.com abstract = True 639338SAndreas.Sandberg@arm.com cxx_header = "mem/cache/prefetch/base.hh" 6413416Sjavier.bueno@metempsy.com cxx_exports = [ 6513416Sjavier.bueno@metempsy.com PyBindMethod("addEventProbe"), 6613416Sjavier.bueno@metempsy.com ] 6710466Sandreas.hansson@arm.com sys = Param.System(Parent.any, "System this prefetcher belongs to") 688831Smrinmoy.ghosh@arm.com 6913422Sodanrc@yahoo.com.br # Get the block size from the parent (system) 7013422Sodanrc@yahoo.com.br block_size = Param.Int(Parent.cache_line_size, "Block size in bytes") 7113422Sodanrc@yahoo.com.br 7210623Smitch.hayenga@arm.com on_miss = Param.Bool(False, "Only notify prefetcher on misses") 7310623Smitch.hayenga@arm.com on_read = Param.Bool(True, "Notify prefetcher on reads") 7410623Smitch.hayenga@arm.com on_write = Param.Bool(True, "Notify prefetcher on writes") 7510623Smitch.hayenga@arm.com on_data = Param.Bool(True, "Notify prefetcher on data accesses") 7610623Smitch.hayenga@arm.com on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses") 7713416Sjavier.bueno@metempsy.com prefetch_on_access = Param.Bool(Parent.prefetch_on_access, 7813416Sjavier.bueno@metempsy.com "Notify the hardware prefetcher on every access (not just misses)") 7913416Sjavier.bueno@metempsy.com 8013416Sjavier.bueno@metempsy.com _events = [] 8113416Sjavier.bueno@metempsy.com def addEvent(self, newObject): 8213416Sjavier.bueno@metempsy.com self._events.append(newObject) 8313416Sjavier.bueno@metempsy.com 8413416Sjavier.bueno@metempsy.com # Override the normal SimObject::regProbeListeners method and 8513416Sjavier.bueno@metempsy.com # register deferred event handlers. 8613416Sjavier.bueno@metempsy.com def regProbeListeners(self): 8713416Sjavier.bueno@metempsy.com for event in self._events: 8813416Sjavier.bueno@metempsy.com event.register() 8913416Sjavier.bueno@metempsy.com self.getCCObject().regProbeListeners() 9013416Sjavier.bueno@metempsy.com 9113416Sjavier.bueno@metempsy.com def listenFromProbe(self, simObj, *probeNames): 9213416Sjavier.bueno@metempsy.com if not isinstance(simObj, SimObject): 9313416Sjavier.bueno@metempsy.com raise TypeError("argument must be of SimObject type") 9413416Sjavier.bueno@metempsy.com if len(probeNames) <= 0: 9513416Sjavier.bueno@metempsy.com raise TypeError("probeNames must have at least one element") 9613416Sjavier.bueno@metempsy.com self.addEvent(HWPProbeEvent(self, simObj, *probeNames)) 9710623Smitch.hayenga@arm.com 9810623Smitch.hayenga@arm.comclass QueuedPrefetcher(BasePrefetcher): 9910623Smitch.hayenga@arm.com type = "QueuedPrefetcher" 10010623Smitch.hayenga@arm.com abstract = True 10110623Smitch.hayenga@arm.com cxx_class = "QueuedPrefetcher" 10210623Smitch.hayenga@arm.com cxx_header = "mem/cache/prefetch/queued.hh" 10310623Smitch.hayenga@arm.com latency = Param.Int(1, "Latency for generated prefetches") 10410623Smitch.hayenga@arm.com queue_size = Param.Int(32, "Maximum number of queued prefetches") 10510623Smitch.hayenga@arm.com queue_squash = Param.Bool(True, "Squash queued prefetch on demand access") 10610623Smitch.hayenga@arm.com queue_filter = Param.Bool(True, "Don't queue redundant prefetches") 10710623Smitch.hayenga@arm.com cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request") 10810623Smitch.hayenga@arm.com 10910623Smitch.hayenga@arm.com tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access") 11010623Smitch.hayenga@arm.com 11110623Smitch.hayenga@arm.comclass StridePrefetcher(QueuedPrefetcher): 1128831Smrinmoy.ghosh@arm.com type = 'StridePrefetcher' 1138831Smrinmoy.ghosh@arm.com cxx_class = 'StridePrefetcher' 1149338SAndreas.Sandberg@arm.com cxx_header = "mem/cache/prefetch/stride.hh" 1158831Smrinmoy.ghosh@arm.com 11613422Sodanrc@yahoo.com.br # Do not consult stride prefetcher on instruction accesses 11713422Sodanrc@yahoo.com.br on_inst = False 11813422Sodanrc@yahoo.com.br 11910623Smitch.hayenga@arm.com max_conf = Param.Int(7, "Maximum confidence level") 12010623Smitch.hayenga@arm.com thresh_conf = Param.Int(4, "Threshold confidence level") 12110623Smitch.hayenga@arm.com min_conf = Param.Int(0, "Minimum confidence level") 12210623Smitch.hayenga@arm.com start_conf = Param.Int(4, "Starting confidence for new entries") 12310623Smitch.hayenga@arm.com 12410623Smitch.hayenga@arm.com table_sets = Param.Int(16, "Number of sets in PC lookup table") 12510623Smitch.hayenga@arm.com table_assoc = Param.Int(4, "Associativity of PC lookup table") 12610623Smitch.hayenga@arm.com use_master_id = Param.Bool(True, "Use master id based history") 12710623Smitch.hayenga@arm.com 12810623Smitch.hayenga@arm.com degree = Param.Int(4, "Number of prefetches to generate") 12910623Smitch.hayenga@arm.com 13013427Sodanrc@yahoo.com.br # Get replacement policy 13113427Sodanrc@yahoo.com.br replacement_policy = Param.BaseReplacementPolicy(RandomRP(), 13213427Sodanrc@yahoo.com.br "Replacement policy") 13313427Sodanrc@yahoo.com.br 13410623Smitch.hayenga@arm.comclass TaggedPrefetcher(QueuedPrefetcher): 1358831Smrinmoy.ghosh@arm.com type = 'TaggedPrefetcher' 1368831Smrinmoy.ghosh@arm.com cxx_class = 'TaggedPrefetcher' 1379338SAndreas.Sandberg@arm.com cxx_header = "mem/cache/prefetch/tagged.hh" 1388831Smrinmoy.ghosh@arm.com 13910623Smitch.hayenga@arm.com degree = Param.Int(2, "Number of prefetches to generate") 140