mshr_queue.hh revision 13351
1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Andreas Sandberg 42 */ 43 44/** @file 45 * Declaration of a structure to manage MSHRs. 46 */ 47 48#ifndef __MEM_CACHE_MSHR_QUEUE_HH__ 49#define __MEM_CACHE_MSHR_QUEUE_HH__ 50 51#include <string> 52 53#include "base/types.hh" 54#include "mem/cache/mshr.hh" 55#include "mem/cache/queue.hh" 56#include "mem/packet.hh" 57 58/** 59 * A Class for maintaining a list of pending and allocated memory requests. 60 */ 61class MSHRQueue : public Queue<MSHR> 62{ 63 private: 64 65 /** 66 * The number of entries to reserve for future demand accesses. 67 * Prevent prefetcher from taking all mshr entries 68 */ 69 const int demandReserve; 70 71 public: 72 73 /** 74 * Create a queue with a given number of entries. 75 * @param num_entrys The number of entries in this queue. 76 * @param reserve The minimum number of entries needed to satisfy 77 * any access. 78 * @param demand_reserve The minimum number of entries needed to satisfy 79 * demand accesses. 80 */ 81 MSHRQueue(const std::string &_label, int num_entries, int reserve, 82 int demand_reserve); 83 84 /** 85 * Allocates a new MSHR for the request and size. This places the request 86 * as the first target in the MSHR. 87 * 88 * @param blk_addr The address of the block. 89 * @param blk_size The number of bytes to request. 90 * @param pkt The original miss. 91 * @param when_ready When should the MSHR be ready to act upon. 92 * @param order The logical order of this MSHR 93 * @param alloc_on_fill Should the cache allocate a block on fill 94 * 95 * @return The a pointer to the MSHR allocated. 96 * 97 * @pre There are free entries. 98 */ 99 MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 100 Tick when_ready, Counter order, bool alloc_on_fill); 101 102 /** 103 * Moves the MSHR to the front of the pending list if it is not 104 * in service. 105 * @param mshr The entry to move. 106 */ 107 void moveToFront(MSHR *mshr); 108 109 /** 110 * Adds a delay to the provided MSHR and moves MSHRs that will be 111 * ready earlier than this entry to the top of the list 112 * 113 * @param mshr that needs to be delayed 114 * @param delay_ticks ticks of the desired delay 115 */ 116 void delay(MSHR *mshr, Tick delay_ticks); 117 118 /** 119 * Mark the given MSHR as in service. This removes the MSHR from the 120 * readyList or deallocates the MSHR if it does not expect a response. 121 * 122 * @param mshr The MSHR to mark in service. 123 * @param pending_modified_resp Whether we expect a modified response 124 * from another cache 125 */ 126 void markInService(MSHR *mshr, bool pending_modified_resp); 127 128 /** 129 * Mark an in service entry as pending, used to resend a request. 130 * @param mshr The MSHR to resend. 131 */ 132 void markPending(MSHR *mshr); 133 134 /** 135 * Deallocate top target, possibly freeing the MSHR 136 * @return if MSHR queue is no longer full 137 */ 138 bool forceDeallocateTarget(MSHR *mshr); 139 140 /** 141 * Returns true if the pending list is not empty. 142 * @return True if there are outstanding requests. 143 */ 144 bool havePending() const 145 { 146 return !readyList.empty(); 147 } 148 149 /** 150 * Returns true if sufficient mshrs for prefetch. 151 * @return True if sufficient mshrs for prefetch. 152 */ 153 bool canPrefetch() const 154 { 155 // @todo we may want to revisit the +1, currently added to 156 // keep regressions unchanged 157 return (allocated < numEntries - (numReserve + 1 + demandReserve)); 158 } 159}; 160 161#endif //__MEM_CACHE_MSHR_QUEUE_HH__ 162