mshr_queue.hh revision 9347
12810SN/A/*
29347SAndreas.Sandberg@arm.com * Copyright (c) 2012 ARM Limited
39347SAndreas.Sandberg@arm.com * All rights reserved.
49347SAndreas.Sandberg@arm.com *
59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall
69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual
79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating
89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software
99347SAndreas.Sandberg@arm.com * licensed hereunder.  You may use the software subject to the license
109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated
119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software,
129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form.
139347SAndreas.Sandberg@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
419347SAndreas.Sandberg@arm.com *          Andreas Sandberg
422810SN/A */
432810SN/A
442810SN/A/** @file
452810SN/A * Declaration of a structure to manage MSHRs.
462810SN/A */
472810SN/A
484626SN/A#ifndef __MEM__CACHE__MISS__MSHR_QUEUE_HH__
494626SN/A#define __MEM__CACHE__MISS__MSHR_QUEUE_HH__
502810SN/A
512810SN/A#include <vector>
524626SN/A
538229Snate@binkert.org#include "mem/cache/mshr.hh"
544626SN/A#include "mem/packet.hh"
559347SAndreas.Sandberg@arm.com#include "sim/drain.hh"
562810SN/A
572810SN/A/**
583374SN/A * A Class for maintaining a list of pending and allocated memory requests.
592810SN/A */
609347SAndreas.Sandberg@arm.comclass MSHRQueue : public Drainable
614626SN/A{
622810SN/A  private:
635314SN/A    /** Local label (for functional print requests) */
645314SN/A    const std::string label;
655314SN/A
662810SN/A    /**  MSHR storage. */
674626SN/A    MSHR *registers;
684626SN/A    /** Holds pointers to all allocated entries. */
692810SN/A    MSHR::List allocatedList;
704626SN/A    /** Holds pointers to entries that haven't been sent to the bus. */
714666SN/A    MSHR::List readyList;
724626SN/A    /** Holds non allocated entries. */
732810SN/A    MSHR::List freeList;
742810SN/A
752810SN/A    // Parameters
762810SN/A    /**
774626SN/A     * The total number of entries in this queue. This number is set as the
784626SN/A     * number of entries requested plus (numReserve - 1). This allows for
794626SN/A     * the same number of effective entries while still maintaining the reserve.
802810SN/A     */
814626SN/A    const int numEntries;
822810SN/A
832810SN/A    /**
844626SN/A     * The number of entries to hold in reserve. This is needed because copy
854626SN/A     * operations can allocate upto 4 entries at one time.
862810SN/A     */
872810SN/A    const int numReserve;
882810SN/A
899347SAndreas.Sandberg@arm.com    /** Drain manager to inform of a completed drain */
909347SAndreas.Sandberg@arm.com    DrainManager *drainManager;
919347SAndreas.Sandberg@arm.com
924666SN/A    MSHR::Iterator addToReadyList(MSHR *mshr);
934666SN/A
944666SN/A
952810SN/A  public:
964626SN/A    /** The number of allocated entries. */
972810SN/A    int allocated;
984626SN/A    /** The number of entries that have been forwarded to the bus. */
994626SN/A    int inServiceEntries;
1004628SN/A    /** The index of this queue within the cache (MSHR queue vs. write
1014628SN/A     * buffer). */
1024628SN/A    const int index;
1032810SN/A
1042810SN/A    /**
1054626SN/A     * Create a queue with a given number of entries.
1064626SN/A     * @param num_entrys The number of entries in this queue.
1074626SN/A     * @param reserve The minimum number of entries needed to satisfy
1084626SN/A     * any access.
1092810SN/A     */
1105314SN/A    MSHRQueue(const std::string &_label, int num_entries, int reserve,
1115314SN/A              int index);
1122810SN/A
1132810SN/A    /** Destructor */
1142810SN/A    ~MSHRQueue();
1152810SN/A
1162810SN/A    /**
1174626SN/A     * Find the first MSHR that matches the provided address.
1182810SN/A     * @param addr The address to find.
1192810SN/A     * @return Pointer to the matching MSHR, null if not found.
1202810SN/A     */
1214626SN/A    MSHR *findMatch(Addr addr) const;
1222810SN/A
1232810SN/A    /**
1244626SN/A     * Find and return all the matching entries in the provided vector.
1252810SN/A     * @param addr The address to find.
1264626SN/A     * @param matches The vector to return pointers to the matching entries.
1272810SN/A     * @return True if any matches are found, false otherwise.
1282810SN/A     * @todo Typedef the vector??
1292810SN/A     */
1302991SN/A    bool findMatches(Addr addr, std::vector<MSHR*>& matches) const;
1312810SN/A
1322810SN/A    /**
1333374SN/A     * Find any pending requests that overlap the given request.
1342982SN/A     * @param pkt The request to find.
1352810SN/A     * @return A pointer to the earliest matching MSHR.
1362810SN/A     */
1374626SN/A    MSHR *findPending(Addr addr, int size) const;
1382810SN/A
1394920SN/A    bool checkFunctional(PacketPtr pkt, Addr blk_addr);
1404920SN/A
1412810SN/A    /**
1423374SN/A     * Allocates a new MSHR for the request and size. This places the request
1432810SN/A     * as the first target in the MSHR.
1442982SN/A     * @param pkt The request to handle.
1452810SN/A     * @param size The number in bytes to fetch from memory.
1462810SN/A     * @return The a pointer to the MSHR allocated.
1472810SN/A     *
1484626SN/A     * @pre There are free entries.
1492810SN/A     */
1504666SN/A    MSHR *allocate(Addr addr, int size, PacketPtr &pkt,
1514666SN/A                   Tick when, Counter order);
1522810SN/A
1532810SN/A    /**
1542810SN/A     * Removes the given MSHR from the queue. This places the MSHR on the
1552810SN/A     * free list.
1562810SN/A     * @param mshr
1572810SN/A     */
1584626SN/A    void deallocate(MSHR *mshr);
1592810SN/A
1602810SN/A    /**
1614626SN/A     * Remove a MSHR from the queue. Returns an iterator into the
1624626SN/A     * allocatedList for faster squash implementation.
1632810SN/A     * @param mshr The MSHR to remove.
1642810SN/A     * @return An iterator to the next entry in the allocatedList.
1652810SN/A     */
1664626SN/A    MSHR::Iterator deallocateOne(MSHR *mshr);
1672810SN/A
1682810SN/A    /**
1694626SN/A     * Moves the MSHR to the front of the pending list if it is not
1704626SN/A     * in service.
1714626SN/A     * @param mshr The entry to move.
1722810SN/A     */
1732810SN/A    void moveToFront(MSHR *mshr);
1742810SN/A
1752810SN/A    /**
1762810SN/A     * Mark the given MSHR as in service. This removes the MSHR from the
1774666SN/A     * readyList. Deallocates the MSHR if it does not expect a response.
1782810SN/A     * @param mshr The MSHR to mark in service.
1792810SN/A     */
1807667Ssteve.reinhardt@amd.com    void markInService(MSHR *mshr, PacketPtr pkt);
1812810SN/A
1822810SN/A    /**
1834626SN/A     * Mark an in service entry as pending, used to resend a request.
1842810SN/A     * @param mshr The MSHR to resend.
1852810SN/A     */
1864626SN/A    void markPending(MSHR *mshr);
1872810SN/A
1882810SN/A    /**
1893374SN/A     * Squash outstanding requests with the given thread number. If a request
1902810SN/A     * is in service, just squashes the targets.
1912982SN/A     * @param threadNum The thread to squash.
1922810SN/A     */
1932812SN/A    void squash(int threadNum);
1942810SN/A
1952810SN/A    /**
1962810SN/A     * Returns true if the pending list is not empty.
1973374SN/A     * @return True if there are outstanding requests.
1982810SN/A     */
1992810SN/A    bool havePending() const
2002810SN/A    {
2014666SN/A        return !readyList.empty();
2022810SN/A    }
2032810SN/A
2042810SN/A    /**
2054626SN/A     * Returns true if there are no free entries.
2062810SN/A     * @return True if this queue is full.
2072810SN/A     */
2082810SN/A    bool isFull() const
2092810SN/A    {
2104626SN/A        return (allocated > numEntries - numReserve);
2112810SN/A    }
2122810SN/A
2132810SN/A    /**
2144666SN/A     * Returns the MSHR at the head of the readyList.
2153374SN/A     * @return The next request to service.
2162810SN/A     */
2174626SN/A    MSHR *getNextMSHR() const
2182810SN/A    {
2197823Ssteve.reinhardt@amd.com        if (readyList.empty() || readyList.front()->readyTime > curTick()) {
2202810SN/A            return NULL;
2212810SN/A        }
2224666SN/A        return readyList.front();
2234666SN/A    }
2244666SN/A
2254871SN/A    Tick nextMSHRReadyTime() const
2264666SN/A    {
2274871SN/A        return readyList.empty() ? MaxTick : readyList.front()->readyTime;
2282810SN/A    }
2299347SAndreas.Sandberg@arm.com
2309347SAndreas.Sandberg@arm.com    unsigned int drain(DrainManager *dm);
2312810SN/A};
2322810SN/A
2334626SN/A#endif //__MEM__CACHE__MISS__MSHR_QUEUE_HH__
234