mshr_queue.hh revision 5314
12810SN/A/* 29347SAndreas.Sandberg@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * Redistribution and use in source and binary forms, with or without 69347SAndreas.Sandberg@arm.com * modification, are permitted provided that the following conditions are 79347SAndreas.Sandberg@arm.com * met: redistributions of source code must retain the above copyright 89347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer; 99347SAndreas.Sandberg@arm.com * redistributions in binary form must reproduce the above copyright 109347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 119347SAndreas.Sandberg@arm.com * documentation and/or other materials provided with the distribution; 129347SAndreas.Sandberg@arm.com * neither the name of the copyright holders nor the names of its 139347SAndreas.Sandberg@arm.com * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** @file 322810SN/A * Declaration of a structure to manage MSHRs. 332810SN/A */ 342810SN/A 352810SN/A#ifndef __MEM__CACHE__MISS__MSHR_QUEUE_HH__ 362810SN/A#define __MEM__CACHE__MISS__MSHR_QUEUE_HH__ 372810SN/A 382810SN/A#include <vector> 392810SN/A 402810SN/A#include "mem/packet.hh" 419347SAndreas.Sandberg@arm.com#include "mem/cache/miss/mshr.hh" 422810SN/A 432810SN/A/** 442810SN/A * A Class for maintaining a list of pending and allocated memory requests. 454626SN/A */ 462810SN/Aclass MSHRQueue 472810SN/A{ 485338Sstever@gmail.com private: 492810SN/A /** Local label (for functional print requests) */ 502810SN/A const std::string label; 512810SN/A 525314SN/A /** MSHR storage. */ 535314SN/A MSHR *registers; 545314SN/A /** Holds pointers to all allocated entries. */ 555314SN/A MSHR::List allocatedList; 569347SAndreas.Sandberg@arm.com /** Holds pointers to entries that haven't been sent to the bus. */ 572810SN/A MSHR::List readyList; 582810SN/A /** Holds non allocated entries. */ 594626SN/A MSHR::List freeList; 604626SN/A 614626SN/A // Parameters 624626SN/A /** 632810SN/A * The total number of entries in this queue. This number is set as the 642810SN/A * number of entries requested plus (numReserve - 1). This allows for 652810SN/A * the same number of effective entries while still maintaining the reserve. 662810SN/A */ 672810SN/A const int numEntries; 682810SN/A 692810SN/A /** 702810SN/A * The number of entries to hold in reserve. This is needed because copy 712810SN/A * operations can allocate upto 4 entries at one time. 724626SN/A */ 732991SN/A const int numReserve; 742810SN/A 752810SN/A MSHR::Iterator addToReadyList(MSHR *mshr); 762810SN/A 772810SN/A 782810SN/A public: 792810SN/A /** The number of allocated entries. */ 802810SN/A int allocated; 812810SN/A /** The number of entries that have been forwarded to the bus. */ 822810SN/A int inServiceEntries; 832810SN/A /** The index of this queue within the cache (MSHR queue vs. write 842810SN/A * buffer). */ 852810SN/A const int index; 862810SN/A 872991SN/A /** 882810SN/A * Create a queue with a given number of entries. 892810SN/A * @param num_entrys The number of entries in this queue. 902810SN/A * @param reserve The minimum number of entries needed to satisfy 912810SN/A * any access. 922810SN/A */ 932810SN/A MSHRQueue(const std::string &_label, int num_entries, int reserve, 942810SN/A int index); 952810SN/A 962810SN/A /** Destructor */ 972810SN/A ~MSHRQueue(); 982810SN/A 992810SN/A /** 1002810SN/A * Find the first MSHR that matches the provided address. 1012810SN/A * @param addr The address to find. 1024920SN/A * @return Pointer to the matching MSHR, null if not found. 1032810SN/A */ 1044920SN/A MSHR *findMatch(Addr addr) const; 1054920SN/A 1064920SN/A /** 1074920SN/A * Find and return all the matching entries in the provided vector. 1085314SN/A * @param addr The address to find. 1094920SN/A * @param matches The vector to return pointers to the matching entries. 1104920SN/A * @return True if any matches are found, false otherwise. 1114920SN/A * @todo Typedef the vector?? 1124920SN/A */ 1134920SN/A bool findMatches(Addr addr, std::vector<MSHR*>& matches) const; 1145314SN/A 1154920SN/A /** 1164920SN/A * Find any pending requests that overlap the given request. 1174920SN/A * @param pkt The request to find. 1185314SN/A * @return A pointer to the earliest matching MSHR. 1194920SN/A */ 1202810SN/A MSHR *findPending(Addr addr, int size) const; 1212810SN/A 1224920SN/A bool checkFunctional(PacketPtr pkt, Addr blk_addr); 1234626SN/A 1244626SN/A /** 1252810SN/A * Allocates a new MSHR for the request and size. This places the request 1264666SN/A * as the first target in the MSHR. 1274666SN/A * @param pkt The request to handle. 1282810SN/A * @param size The number in bytes to fetch from memory. 1292810SN/A * @return The a pointer to the MSHR allocated. 1304626SN/A * 1314626SN/A * @pre There are free entries. 1322810SN/A */ 1332810SN/A MSHR *allocate(Addr addr, int size, PacketPtr &pkt, 1342810SN/A Tick when, Counter order); 1354626SN/A 1362810SN/A /** 1372810SN/A * Removes the given MSHR from the queue. This places the MSHR on the 1382810SN/A * free list. 1392810SN/A * @param mshr 1402810SN/A */ 1412810SN/A void deallocate(MSHR *mshr); 1422810SN/A 1434666SN/A /** 1444666SN/A * Remove a MSHR from the queue. Returns an iterator into the 1454666SN/A * allocatedList for faster squash implementation. 1464666SN/A * @param mshr The MSHR to remove. 1474871SN/A * @return An iterator to the next entry in the allocatedList. 1484666SN/A */ 1494666SN/A MSHR::Iterator deallocateOne(MSHR *mshr); 1504666SN/A 1514666SN/A /** 1524666SN/A * Moves the MSHR to the front of the pending list if it is not 1534666SN/A * in service. 1544871SN/A * @param mshr The entry to move. 1554666SN/A */ 1564666SN/A void moveToFront(MSHR *mshr); 1574666SN/A 1584666SN/A /** 1594904SN/A * Mark the given MSHR as in service. This removes the MSHR from the 1604666SN/A * readyList. Deallocates the MSHR if it does not expect a response. 1614666SN/A * @param mshr The MSHR to mark in service. 1624666SN/A */ 1634626SN/A void markInService(MSHR *mshr); 1644666SN/A 1654666SN/A /** 1662810SN/A * Mark an in service entry as pending, used to resend a request. 1673149SN/A * @param mshr The MSHR to resend. 1682810SN/A */ 1692810SN/A void markPending(MSHR *mshr); 1702810SN/A 1712810SN/A /** 1724666SN/A * Squash outstanding requests with the given thread number. If a request 1732810SN/A * is in service, just squashes the targets. 1744666SN/A * @param threadNum The thread to squash. 1752810SN/A */ 1762810SN/A void squash(int threadNum); 1772810SN/A 1782810SN/A /** 1792810SN/A * Returns true if the pending list is not empty. 1802810SN/A * @return True if there are outstanding requests. 1812810SN/A */ 1824626SN/A bool havePending() const 1832810SN/A { 1842810SN/A return !readyList.empty(); 1852810SN/A } 1862810SN/A 1872810SN/A /** 1884626SN/A * Returns true if there are no free entries. 1892810SN/A * @return True if this queue is full. 1902810SN/A */ 1912810SN/A bool isFull() const 1922810SN/A { 1932810SN/A return (allocated > numEntries - numReserve); 1944626SN/A } 1952810SN/A 1964666SN/A /** 1972810SN/A * Returns the MSHR at the head of the readyList. 1982810SN/A * @return The next request to service. 1999347SAndreas.Sandberg@arm.com */ 2009347SAndreas.Sandberg@arm.com MSHR *getNextMSHR() const 2019347SAndreas.Sandberg@arm.com { 2029347SAndreas.Sandberg@arm.com if (readyList.empty() || readyList.front()->readyTime > curTick) { 2039347SAndreas.Sandberg@arm.com return NULL; 2049347SAndreas.Sandberg@arm.com } 2059347SAndreas.Sandberg@arm.com return readyList.front(); 2062810SN/A } 2072810SN/A 2082810SN/A Tick nextMSHRReadyTime() const 2092810SN/A { 2102810SN/A return readyList.empty() ? MaxTick : readyList.front()->readyTime; 2112810SN/A } 2122810SN/A}; 2132810SN/A 2144666SN/A#endif //__MEM__CACHE__MISS__MSHR_QUEUE_HH__ 2154666SN/A