mshr_queue.hh revision 12727
12810SN/A/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 419347SAndreas.Sandberg@arm.com * Andreas Sandberg 422810SN/A */ 432810SN/A 442810SN/A/** @file 452810SN/A * Declaration of a structure to manage MSHRs. 462810SN/A */ 472810SN/A 4810764Sandreas.hansson@arm.com#ifndef __MEM_CACHE_MSHR_QUEUE_HH__ 4910764Sandreas.hansson@arm.com#define __MEM_CACHE_MSHR_QUEUE_HH__ 502810SN/A 5112727Snikos.nikoleris@arm.com#include <string> 524626SN/A 5312727Snikos.nikoleris@arm.com#include "base/types.hh" 548229Snate@binkert.org#include "mem/cache/mshr.hh" 5511375Sandreas.hansson@arm.com#include "mem/cache/queue.hh" 5612727Snikos.nikoleris@arm.com#include "mem/packet.hh" 572810SN/A 582810SN/A/** 593374SN/A * A Class for maintaining a list of pending and allocated memory requests. 602810SN/A */ 6111375Sandreas.hansson@arm.comclass MSHRQueue : public Queue<MSHR> 624626SN/A{ 632810SN/A private: 642810SN/A 6510622Smitch.hayenga@arm.com /** 6610622Smitch.hayenga@arm.com * The number of entries to reserve for future demand accesses. 6710622Smitch.hayenga@arm.com * Prevent prefetcher from taking all mshr entries 6810622Smitch.hayenga@arm.com */ 6910622Smitch.hayenga@arm.com const int demandReserve; 7010622Smitch.hayenga@arm.com 712810SN/A public: 722810SN/A 732810SN/A /** 744626SN/A * Create a queue with a given number of entries. 754626SN/A * @param num_entrys The number of entries in this queue. 764626SN/A * @param reserve The minimum number of entries needed to satisfy 774626SN/A * any access. 7810622Smitch.hayenga@arm.com * @param demand_reserve The minimum number of entries needed to satisfy 7910622Smitch.hayenga@arm.com * demand accesses. 802810SN/A */ 815314SN/A MSHRQueue(const std::string &_label, int num_entries, int reserve, 8211375Sandreas.hansson@arm.com int demand_reserve); 834920SN/A 842810SN/A /** 853374SN/A * Allocates a new MSHR for the request and size. This places the request 862810SN/A * as the first target in the MSHR. 8710764Sandreas.hansson@arm.com * 8810764Sandreas.hansson@arm.com * @param blk_addr The address of the block. 8910764Sandreas.hansson@arm.com * @param blk_size The number of bytes to request. 9010764Sandreas.hansson@arm.com * @param pkt The original miss. 9110764Sandreas.hansson@arm.com * @param when_ready When should the MSHR be ready to act upon. 9210764Sandreas.hansson@arm.com * @param order The logical order of this MSHR 9311197Sandreas.hansson@arm.com * @param alloc_on_fill Should the cache allocate a block on fill 9410764Sandreas.hansson@arm.com * 952810SN/A * @return The a pointer to the MSHR allocated. 962810SN/A * 974626SN/A * @pre There are free entries. 982810SN/A */ 9910764Sandreas.hansson@arm.com MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 10011197Sandreas.hansson@arm.com Tick when_ready, Counter order, bool alloc_on_fill); 1012810SN/A 1022810SN/A /** 1034626SN/A * Moves the MSHR to the front of the pending list if it is not 1044626SN/A * in service. 1054626SN/A * @param mshr The entry to move. 1062810SN/A */ 1072810SN/A void moveToFront(MSHR *mshr); 1082810SN/A 1092810SN/A /** 1102810SN/A * Mark the given MSHR as in service. This removes the MSHR from the 11110679Sandreas.hansson@arm.com * readyList or deallocates the MSHR if it does not expect a response. 11210679Sandreas.hansson@arm.com * 1132810SN/A * @param mshr The MSHR to mark in service. 11411284Sandreas.hansson@arm.com * @param pending_modified_resp Whether we expect a modified response 11511284Sandreas.hansson@arm.com * from another cache 1162810SN/A */ 11711284Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_modified_resp); 1182810SN/A 1192810SN/A /** 1204626SN/A * Mark an in service entry as pending, used to resend a request. 1212810SN/A * @param mshr The MSHR to resend. 1222810SN/A */ 1234626SN/A void markPending(MSHR *mshr); 1242810SN/A 1252810SN/A /** 12610192Smitch.hayenga@arm.com * Deallocate top target, possibly freeing the MSHR 12710192Smitch.hayenga@arm.com * @return if MSHR queue is no longer full 12810192Smitch.hayenga@arm.com */ 12910192Smitch.hayenga@arm.com bool forceDeallocateTarget(MSHR *mshr); 13010192Smitch.hayenga@arm.com 13110192Smitch.hayenga@arm.com /** 1322810SN/A * Returns true if the pending list is not empty. 1333374SN/A * @return True if there are outstanding requests. 1342810SN/A */ 1352810SN/A bool havePending() const 1362810SN/A { 1374666SN/A return !readyList.empty(); 1382810SN/A } 1392810SN/A 1402810SN/A /** 14110622Smitch.hayenga@arm.com * Returns true if sufficient mshrs for prefetch. 14210622Smitch.hayenga@arm.com * @return True if sufficient mshrs for prefetch. 14310622Smitch.hayenga@arm.com */ 14410622Smitch.hayenga@arm.com bool canPrefetch() const 14510622Smitch.hayenga@arm.com { 14611377Sandreas.hansson@arm.com // @todo we may want to revisit the +1, currently added to 14711377Sandreas.hansson@arm.com // keep regressions unchanged 14811377Sandreas.hansson@arm.com return (allocated < numEntries - (numReserve + 1 + demandReserve)); 14910622Smitch.hayenga@arm.com } 1502810SN/A}; 1512810SN/A 15210764Sandreas.hansson@arm.com#endif //__MEM_CACHE_MSHR_QUEUE_HH__ 153