mshr_queue.hh revision 11377
12810SN/A/*
211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited
39347SAndreas.Sandberg@arm.com * All rights reserved.
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129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form.
139347SAndreas.Sandberg@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
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202810SN/A * notice, this list of conditions and the following disclaimer;
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272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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392810SN/A *
402810SN/A * Authors: Erik Hallnor
419347SAndreas.Sandberg@arm.com *          Andreas Sandberg
422810SN/A */
432810SN/A
442810SN/A/** @file
452810SN/A * Declaration of a structure to manage MSHRs.
462810SN/A */
472810SN/A
4810764Sandreas.hansson@arm.com#ifndef __MEM_CACHE_MSHR_QUEUE_HH__
4910764Sandreas.hansson@arm.com#define __MEM_CACHE_MSHR_QUEUE_HH__
502810SN/A
512810SN/A#include <vector>
524626SN/A
538229Snate@binkert.org#include "mem/cache/mshr.hh"
5411375Sandreas.hansson@arm.com#include "mem/cache/queue.hh"
552810SN/A
562810SN/A/**
573374SN/A * A Class for maintaining a list of pending and allocated memory requests.
582810SN/A */
5911375Sandreas.hansson@arm.comclass MSHRQueue : public Queue<MSHR>
604626SN/A{
612810SN/A  private:
622810SN/A
6310622Smitch.hayenga@arm.com    /**
6410622Smitch.hayenga@arm.com     * The number of entries to reserve for future demand accesses.
6510622Smitch.hayenga@arm.com     * Prevent prefetcher from taking all mshr entries
6610622Smitch.hayenga@arm.com     */
6710622Smitch.hayenga@arm.com    const int demandReserve;
6810622Smitch.hayenga@arm.com
692810SN/A  public:
702810SN/A
712810SN/A    /**
724626SN/A     * Create a queue with a given number of entries.
734626SN/A     * @param num_entrys The number of entries in this queue.
744626SN/A     * @param reserve The minimum number of entries needed to satisfy
754626SN/A     * any access.
7610622Smitch.hayenga@arm.com     * @param demand_reserve The minimum number of entries needed to satisfy
7710622Smitch.hayenga@arm.com     * demand accesses.
782810SN/A     */
795314SN/A    MSHRQueue(const std::string &_label, int num_entries, int reserve,
8011375Sandreas.hansson@arm.com              int demand_reserve);
814920SN/A
822810SN/A    /**
833374SN/A     * Allocates a new MSHR for the request and size. This places the request
842810SN/A     * as the first target in the MSHR.
8510764Sandreas.hansson@arm.com     *
8610764Sandreas.hansson@arm.com     * @param blk_addr The address of the block.
8710764Sandreas.hansson@arm.com     * @param blk_size The number of bytes to request.
8810764Sandreas.hansson@arm.com     * @param pkt The original miss.
8910764Sandreas.hansson@arm.com     * @param when_ready When should the MSHR be ready to act upon.
9010764Sandreas.hansson@arm.com     * @param order The logical order of this MSHR
9111197Sandreas.hansson@arm.com     * @param alloc_on_fill Should the cache allocate a block on fill
9210764Sandreas.hansson@arm.com     *
932810SN/A     * @return The a pointer to the MSHR allocated.
942810SN/A     *
954626SN/A     * @pre There are free entries.
962810SN/A     */
9710764Sandreas.hansson@arm.com    MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
9811197Sandreas.hansson@arm.com                   Tick when_ready, Counter order, bool alloc_on_fill);
992810SN/A
1002810SN/A    /**
1014626SN/A     * Moves the MSHR to the front of the pending list if it is not
1024626SN/A     * in service.
1034626SN/A     * @param mshr The entry to move.
1042810SN/A     */
1052810SN/A    void moveToFront(MSHR *mshr);
1062810SN/A
1072810SN/A    /**
1082810SN/A     * Mark the given MSHR as in service. This removes the MSHR from the
10910679Sandreas.hansson@arm.com     * readyList or deallocates the MSHR if it does not expect a response.
11010679Sandreas.hansson@arm.com     *
1112810SN/A     * @param mshr The MSHR to mark in service.
11211284Sandreas.hansson@arm.com     * @param pending_modified_resp Whether we expect a modified response
11311284Sandreas.hansson@arm.com     *                              from another cache
1142810SN/A     */
11511284Sandreas.hansson@arm.com    void markInService(MSHR *mshr, bool pending_modified_resp);
1162810SN/A
1172810SN/A    /**
1184626SN/A     * Mark an in service entry as pending, used to resend a request.
1192810SN/A     * @param mshr The MSHR to resend.
1202810SN/A     */
1214626SN/A    void markPending(MSHR *mshr);
1222810SN/A
1232810SN/A    /**
12410192Smitch.hayenga@arm.com     * Deallocate top target, possibly freeing the MSHR
12510192Smitch.hayenga@arm.com     * @return if MSHR queue is no longer full
12610192Smitch.hayenga@arm.com     */
12710192Smitch.hayenga@arm.com    bool forceDeallocateTarget(MSHR *mshr);
12810192Smitch.hayenga@arm.com
12910192Smitch.hayenga@arm.com    /**
1302810SN/A     * Returns true if the pending list is not empty.
1313374SN/A     * @return True if there are outstanding requests.
1322810SN/A     */
1332810SN/A    bool havePending() const
1342810SN/A    {
1354666SN/A        return !readyList.empty();
1362810SN/A    }
1372810SN/A
1382810SN/A    /**
13910622Smitch.hayenga@arm.com     * Returns true if sufficient mshrs for prefetch.
14010622Smitch.hayenga@arm.com     * @return True if sufficient mshrs for prefetch.
14110622Smitch.hayenga@arm.com     */
14210622Smitch.hayenga@arm.com    bool canPrefetch() const
14310622Smitch.hayenga@arm.com    {
14411377Sandreas.hansson@arm.com        // @todo we may want to revisit the +1, currently added to
14511377Sandreas.hansson@arm.com        // keep regressions unchanged
14611377Sandreas.hansson@arm.com        return (allocated < numEntries - (numReserve + 1 + demandReserve));
14710622Smitch.hayenga@arm.com    }
1482810SN/A};
1492810SN/A
15010764Sandreas.hansson@arm.com#endif //__MEM_CACHE_MSHR_QUEUE_HH__
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