mshr_queue.hh revision 10764
12810SN/A/* 210764Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 419347SAndreas.Sandberg@arm.com * Andreas Sandberg 422810SN/A */ 432810SN/A 442810SN/A/** @file 452810SN/A * Declaration of a structure to manage MSHRs. 462810SN/A */ 472810SN/A 4810764Sandreas.hansson@arm.com#ifndef __MEM_CACHE_MSHR_QUEUE_HH__ 4910764Sandreas.hansson@arm.com#define __MEM_CACHE_MSHR_QUEUE_HH__ 502810SN/A 512810SN/A#include <vector> 524626SN/A 538229Snate@binkert.org#include "mem/cache/mshr.hh" 544626SN/A#include "mem/packet.hh" 559347SAndreas.Sandberg@arm.com#include "sim/drain.hh" 562810SN/A 572810SN/A/** 583374SN/A * A Class for maintaining a list of pending and allocated memory requests. 592810SN/A */ 609347SAndreas.Sandberg@arm.comclass MSHRQueue : public Drainable 614626SN/A{ 622810SN/A private: 635314SN/A /** Local label (for functional print requests) */ 645314SN/A const std::string label; 655314SN/A 662810SN/A // Parameters 672810SN/A /** 684626SN/A * The total number of entries in this queue. This number is set as the 694626SN/A * number of entries requested plus (numReserve - 1). This allows for 704626SN/A * the same number of effective entries while still maintaining the reserve. 712810SN/A */ 724626SN/A const int numEntries; 732810SN/A 742810SN/A /** 754626SN/A * The number of entries to hold in reserve. This is needed because copy 764626SN/A * operations can allocate upto 4 entries at one time. 772810SN/A */ 782810SN/A const int numReserve; 792810SN/A 8010622Smitch.hayenga@arm.com /** 8110622Smitch.hayenga@arm.com * The number of entries to reserve for future demand accesses. 8210622Smitch.hayenga@arm.com * Prevent prefetcher from taking all mshr entries 8310622Smitch.hayenga@arm.com */ 8410622Smitch.hayenga@arm.com const int demandReserve; 8510622Smitch.hayenga@arm.com 869725Sandreas.hansson@arm.com /** MSHR storage. */ 879725Sandreas.hansson@arm.com std::vector<MSHR> registers; 889725Sandreas.hansson@arm.com /** Holds pointers to all allocated entries. */ 899725Sandreas.hansson@arm.com MSHR::List allocatedList; 909725Sandreas.hansson@arm.com /** Holds pointers to entries that haven't been sent to the bus. */ 919725Sandreas.hansson@arm.com MSHR::List readyList; 929725Sandreas.hansson@arm.com /** Holds non allocated entries. */ 939725Sandreas.hansson@arm.com MSHR::List freeList; 949725Sandreas.hansson@arm.com 959347SAndreas.Sandberg@arm.com /** Drain manager to inform of a completed drain */ 969347SAndreas.Sandberg@arm.com DrainManager *drainManager; 979347SAndreas.Sandberg@arm.com 984666SN/A MSHR::Iterator addToReadyList(MSHR *mshr); 994666SN/A 1004666SN/A 1012810SN/A public: 1024626SN/A /** The number of allocated entries. */ 1032810SN/A int allocated; 1044626SN/A /** The number of entries that have been forwarded to the bus. */ 1054626SN/A int inServiceEntries; 1064628SN/A /** The index of this queue within the cache (MSHR queue vs. write 1074628SN/A * buffer). */ 1084628SN/A const int index; 1092810SN/A 1102810SN/A /** 1114626SN/A * Create a queue with a given number of entries. 1124626SN/A * @param num_entrys The number of entries in this queue. 1134626SN/A * @param reserve The minimum number of entries needed to satisfy 1144626SN/A * any access. 11510622Smitch.hayenga@arm.com * @param demand_reserve The minimum number of entries needed to satisfy 11610622Smitch.hayenga@arm.com * demand accesses. 1172810SN/A */ 1185314SN/A MSHRQueue(const std::string &_label, int num_entries, int reserve, 11910622Smitch.hayenga@arm.com int demand_reserve, int index); 1202810SN/A 1212810SN/A /** 1224626SN/A * Find the first MSHR that matches the provided address. 12310764Sandreas.hansson@arm.com * @param blk_addr The block address to find. 12410028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1252810SN/A * @return Pointer to the matching MSHR, null if not found. 1262810SN/A */ 12710764Sandreas.hansson@arm.com MSHR *findMatch(Addr blk_addr, bool is_secure) const; 1282810SN/A 1292810SN/A /** 1304626SN/A * Find and return all the matching entries in the provided vector. 13110764Sandreas.hansson@arm.com * @param blk_addr The block address to find. 13210028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1334626SN/A * @param matches The vector to return pointers to the matching entries. 1342810SN/A * @return True if any matches are found, false otherwise. 1352810SN/A */ 13610764Sandreas.hansson@arm.com bool findMatches(Addr blk_addr, bool is_secure, 13710028SGiacomo.Gabrielli@arm.com std::vector<MSHR*>& matches) const; 1382810SN/A 1392810SN/A /** 1403374SN/A * Find any pending requests that overlap the given request. 14110764Sandreas.hansson@arm.com * @param blk_addr Block address. 14210028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1432810SN/A * @return A pointer to the earliest matching MSHR. 1442810SN/A */ 14510764Sandreas.hansson@arm.com MSHR *findPending(Addr blk_addr, bool is_secure) const; 1462810SN/A 1474920SN/A bool checkFunctional(PacketPtr pkt, Addr blk_addr); 1484920SN/A 1492810SN/A /** 1503374SN/A * Allocates a new MSHR for the request and size. This places the request 1512810SN/A * as the first target in the MSHR. 15210764Sandreas.hansson@arm.com * 15310764Sandreas.hansson@arm.com * @param blk_addr The address of the block. 15410764Sandreas.hansson@arm.com * @param blk_size The number of bytes to request. 15510764Sandreas.hansson@arm.com * @param pkt The original miss. 15610764Sandreas.hansson@arm.com * @param when_ready When should the MSHR be ready to act upon. 15710764Sandreas.hansson@arm.com * @param order The logical order of this MSHR 15810764Sandreas.hansson@arm.com * 1592810SN/A * @return The a pointer to the MSHR allocated. 1602810SN/A * 1614626SN/A * @pre There are free entries. 1622810SN/A */ 16310764Sandreas.hansson@arm.com MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 16410764Sandreas.hansson@arm.com Tick when_ready, Counter order); 1652810SN/A 1662810SN/A /** 1672810SN/A * Removes the given MSHR from the queue. This places the MSHR on the 1682810SN/A * free list. 1692810SN/A * @param mshr 1702810SN/A */ 1714626SN/A void deallocate(MSHR *mshr); 1722810SN/A 1732810SN/A /** 1744626SN/A * Remove a MSHR from the queue. Returns an iterator into the 1754626SN/A * allocatedList for faster squash implementation. 1762810SN/A * @param mshr The MSHR to remove. 1772810SN/A * @return An iterator to the next entry in the allocatedList. 1782810SN/A */ 1794626SN/A MSHR::Iterator deallocateOne(MSHR *mshr); 1802810SN/A 1812810SN/A /** 1824626SN/A * Moves the MSHR to the front of the pending list if it is not 1834626SN/A * in service. 1844626SN/A * @param mshr The entry to move. 1852810SN/A */ 1862810SN/A void moveToFront(MSHR *mshr); 1872810SN/A 1882810SN/A /** 1892810SN/A * Mark the given MSHR as in service. This removes the MSHR from the 19010679Sandreas.hansson@arm.com * readyList or deallocates the MSHR if it does not expect a response. 19110679Sandreas.hansson@arm.com * 1922810SN/A * @param mshr The MSHR to mark in service. 19310679Sandreas.hansson@arm.com * @param pending_dirty_resp Whether we expect a dirty response 19410679Sandreas.hansson@arm.com * from another cache 1952810SN/A */ 19610679Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_dirty_resp); 1972810SN/A 1982810SN/A /** 1994626SN/A * Mark an in service entry as pending, used to resend a request. 2002810SN/A * @param mshr The MSHR to resend. 2012810SN/A */ 2024626SN/A void markPending(MSHR *mshr); 2032810SN/A 2042810SN/A /** 2053374SN/A * Squash outstanding requests with the given thread number. If a request 2062810SN/A * is in service, just squashes the targets. 2072982SN/A * @param threadNum The thread to squash. 2082810SN/A */ 2092812SN/A void squash(int threadNum); 2102810SN/A 2112810SN/A /** 21210192Smitch.hayenga@arm.com * Deallocate top target, possibly freeing the MSHR 21310192Smitch.hayenga@arm.com * @return if MSHR queue is no longer full 21410192Smitch.hayenga@arm.com */ 21510192Smitch.hayenga@arm.com bool forceDeallocateTarget(MSHR *mshr); 21610192Smitch.hayenga@arm.com 21710192Smitch.hayenga@arm.com /** 2182810SN/A * Returns true if the pending list is not empty. 2193374SN/A * @return True if there are outstanding requests. 2202810SN/A */ 2212810SN/A bool havePending() const 2222810SN/A { 2234666SN/A return !readyList.empty(); 2242810SN/A } 2252810SN/A 2262810SN/A /** 2274626SN/A * Returns true if there are no free entries. 2282810SN/A * @return True if this queue is full. 2292810SN/A */ 2302810SN/A bool isFull() const 2312810SN/A { 2324626SN/A return (allocated > numEntries - numReserve); 2332810SN/A } 2342810SN/A 2352810SN/A /** 23610622Smitch.hayenga@arm.com * Returns true if sufficient mshrs for prefetch. 23710622Smitch.hayenga@arm.com * @return True if sufficient mshrs for prefetch. 23810622Smitch.hayenga@arm.com */ 23910622Smitch.hayenga@arm.com bool canPrefetch() const 24010622Smitch.hayenga@arm.com { 24110622Smitch.hayenga@arm.com return (allocated < numEntries - (numReserve + demandReserve)); 24210622Smitch.hayenga@arm.com } 24310622Smitch.hayenga@arm.com 24410622Smitch.hayenga@arm.com /** 2454666SN/A * Returns the MSHR at the head of the readyList. 2463374SN/A * @return The next request to service. 2472810SN/A */ 2484626SN/A MSHR *getNextMSHR() const 2492810SN/A { 2507823Ssteve.reinhardt@amd.com if (readyList.empty() || readyList.front()->readyTime > curTick()) { 2512810SN/A return NULL; 2522810SN/A } 2534666SN/A return readyList.front(); 2544666SN/A } 2554666SN/A 2564871SN/A Tick nextMSHRReadyTime() const 2574666SN/A { 2584871SN/A return readyList.empty() ? MaxTick : readyList.front()->readyTime; 2592810SN/A } 2609347SAndreas.Sandberg@arm.com 2619347SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 2622810SN/A}; 2632810SN/A 26410764Sandreas.hansson@arm.com#endif //__MEM_CACHE_MSHR_QUEUE_HH__ 265