mshr_queue.cc revision 4871
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** @file 322810SN/A * Definition of MSHRQueue class functions. 332810SN/A */ 342810SN/A 352810SN/A#include "mem/cache/miss/mshr_queue.hh" 363348SN/A 373348SN/Ausing namespace std; 388232Snate@binkert.org 395338Sstever@gmail.comMSHRQueue::MSHRQueue(int num_entries, int reserve, int _index) 405338Sstever@gmail.com : numEntries(num_entries + reserve - 1), numReserve(reserve), 412810SN/A index(_index) 422810SN/A{ 432810SN/A allocated = 0; 444965SN/A inServiceEntries = 0; 456122SSteve.Reinhardt@amd.com registers = new MSHR[numEntries]; 465314SN/A for (int i = 0; i < numEntries; ++i) { 478736Sandreas.hansson@arm.com registers[i].queue = this; 482810SN/A freeList.push_back(®isters[i]); 494475SN/A } 504475SN/A} 514475SN/A 525034SN/AMSHRQueue::~MSHRQueue() 535034SN/A{ 545314SN/A delete [] registers; 555314SN/A} 564628SN/A 575034SN/AMSHR * 585034SN/AMSHRQueue::findMatch(Addr addr) const 595034SN/A{ 606122SSteve.Reinhardt@amd.com MSHR::ConstIterator i = allocatedList.begin(); 618134SAli.Saidi@ARM.com MSHR::ConstIterator end = allocatedList.end(); 624626SN/A for (; i != end; ++i) { 634626SN/A MSHR *mshr = *i; 645034SN/A if (mshr->addr == addr) { 656122SSteve.Reinhardt@amd.com return mshr; 666978SLisa.Hsu@amd.com } 676978SLisa.Hsu@amd.com } 684458SN/A return NULL; 692810SN/A} 702810SN/A 715314SN/Abool 725314SN/AMSHRQueue::findMatches(Addr addr, vector<MSHR*>& matches) const 735314SN/A{ 745314SN/A // Need an empty vector 755314SN/A assert(matches.empty()); 765314SN/A bool retval = false; 775314SN/A MSHR::ConstIterator i = allocatedList.begin(); 785314SN/A MSHR::ConstIterator end = allocatedList.end(); 795314SN/A for (; i != end; ++i) { 805314SN/A MSHR *mshr = *i; 815314SN/A if (mshr->addr == addr) { 826227Snate@binkert.org retval = true; 836227Snate@binkert.org matches.push_back(mshr); 842810SN/A } 852810SN/A } 862810SN/A return retval; 872810SN/A 883606SN/A} 894458SN/A 904458SN/AMSHR * 913013SN/AMSHRQueue::findPending(Addr addr, int size) const 923236SN/A{ 934458SN/A MSHR::ConstIterator i = readyList.begin(); 944458SN/A MSHR::ConstIterator end = readyList.end(); 954458SN/A for (; i != end; ++i) { 963246SN/A MSHR *mshr = *i; 973309SN/A if (mshr->addr < addr) { 983013SN/A if (mshr->addr + mshr->size > addr) { 992810SN/A return mshr; 1002810SN/A } 1013013SN/A } else { 1023013SN/A if (addr + size > mshr->addr) { 1032810SN/A return mshr; 1043013SN/A } 1053013SN/A } 1062810SN/A } 1072810SN/A return NULL; 1082810SN/A} 1092810SN/A 1102810SN/A 1113013SN/AMSHR::Iterator 1123013SN/AMSHRQueue::addToReadyList(MSHR *mshr) 1133013SN/A{ 1142897SN/A if (readyList.empty() || readyList.back()->readyTime <= mshr->readyTime) { 1152897SN/A return readyList.insert(readyList.end(), mshr); 1163013SN/A } 1172897SN/A 1184666SN/A MSHR::Iterator i = readyList.begin(); 1194666SN/A MSHR::Iterator end = readyList.end(); 1208708Sandreas.hansson@arm.com for (; i != end; ++i) { 1212897SN/A if ((*i)->readyTime > mshr->readyTime) { 1222810SN/A return readyList.insert(i, mshr); 1232810SN/A } 1242844SN/A } 1252810SN/A assert(false); 1262858SN/A} 1272858SN/A 1282858SN/A 1292858SN/AMSHR * 1308711Sandreas.hansson@arm.comMSHRQueue::allocate(Addr addr, int size, PacketPtr &pkt, 1312858SN/A Tick when, Counter order) 1322858SN/A{ 1334628SN/A assert(!freeList.empty()); 1342858SN/A MSHR *mshr = freeList.front(); 1352810SN/A assert(mshr->getNumTargets() == 0); 1362810SN/A freeList.pop_front(); 1372810SN/A 1382810SN/A mshr->allocate(addr, size, pkt, when, order); 1392810SN/A mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); 1404022SN/A mshr->readyIter = addToReadyList(mshr); 1414022SN/A 1424022SN/A allocated += 1; 1432810SN/A return mshr; 1442810SN/A} 1456978SLisa.Hsu@amd.com 1466978SLisa.Hsu@amd.com 1476978SLisa.Hsu@amd.comvoid 1486978SLisa.Hsu@amd.comMSHRQueue::deallocate(MSHR *mshr) 1496978SLisa.Hsu@amd.com{ 1502810SN/A deallocateOne(mshr); 1512810SN/A} 1522810SN/A 1532810SN/AMSHR::Iterator 1542810SN/AMSHRQueue::deallocateOne(MSHR *mshr) 1552810SN/A{ 1564871SN/A MSHR::Iterator retval = allocatedList.erase(mshr->allocIter); 1574871SN/A freeList.push_front(mshr); 1584871SN/A allocated--; 1594871SN/A if (mshr->inService) { 1604871SN/A inServiceEntries--; 1614871SN/A } else { 1624871SN/A readyList.erase(mshr->readyIter); 1634871SN/A } 1644871SN/A mshr->deallocate(); 1654871SN/A return retval; 1662810SN/A} 1672810SN/A 1682810SN/Avoid 1692810SN/AMSHRQueue::moveToFront(MSHR *mshr) 1702810SN/A{ 1714871SN/A if (!mshr->inService) { 1722810SN/A assert(mshr == *(mshr->readyIter)); 1732810SN/A readyList.erase(mshr->readyIter); 1742810SN/A mshr->readyIter = readyList.insert(readyList.begin(), mshr); 1752810SN/A } 1762810SN/A} 1772810SN/A 1784871SN/Avoid 1792810SN/AMSHRQueue::markInService(MSHR *mshr) 1802810SN/A{ 1814022SN/A assert(!mshr->inService); 1824022SN/A if (mshr->isSimpleForward()) { 1834022SN/A // we just forwarded the request packet & don't expect a 1842810SN/A // response, so get rid of it 1852810SN/A assert(mshr->getNumTargets() == 1); 1866978SLisa.Hsu@amd.com mshr->popTarget(); 1876978SLisa.Hsu@amd.com deallocate(mshr); 1886978SLisa.Hsu@amd.com return; 1896978SLisa.Hsu@amd.com } 1906978SLisa.Hsu@amd.com mshr->inService = true; 1912810SN/A readyList.erase(mshr->readyIter); 1922810SN/A //mshr->readyIter = NULL; 1932810SN/A inServiceEntries += 1; 1942810SN/A //readyList.pop_front(); 1952810SN/A} 1962810SN/A 1972810SN/Avoid 1982810SN/AMSHRQueue::markPending(MSHR *mshr) 1992810SN/A{ 2002810SN/A assert(mshr->inService); 2012810SN/A mshr->inService = false; 2024871SN/A --inServiceEntries; 2032810SN/A /** 2042810SN/A * @ todo might want to add rerequests to front of pending list for 2052810SN/A * performance. 2062810SN/A */ 2072810SN/A mshr->readyIter = addToReadyList(mshr); 2082810SN/A} 2094871SN/A 2102810SN/Avoid 2112810SN/AMSHRQueue::squash(int threadNum) 2124022SN/A{ 2134022SN/A MSHR::Iterator i = allocatedList.begin(); 2144022SN/A MSHR::Iterator end = allocatedList.end(); 2152810SN/A for (; i != end;) { 2162810SN/A MSHR *mshr = *i; 2172810SN/A if (mshr->threadNum == threadNum) { 2182810SN/A while (mshr->hasTargets()) { 2192810SN/A mshr->popTarget(); 2202810SN/A assert(0/*target->req->getThreadNum()*/ == threadNum); 2212810SN/A } 2222810SN/A assert(!mshr->hasTargets()); 2232810SN/A assert(mshr->ntargets==0); 2242810SN/A if (!mshr->inService) { 2252810SN/A i = deallocateOne(mshr); 2262810SN/A } else { 2272810SN/A //mshr->pkt->flags &= ~CACHE_LINE_FILL; 2282810SN/A ++i; 2294871SN/A } 2302810SN/A } else { 2312810SN/A ++i; 2322810SN/A } 2332810SN/A } 2342810SN/A} 2352810SN/A