mshr.hh revision 9264
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 */ 30 31/** 32 * @file 33 * Miss Status and Handling Register (MSHR) declaration. 34 */ 35 36#ifndef __MSHR_HH__ 37#define __MSHR_HH__ 38 39#include <list> 40 41#include "base/printable.hh" 42#include "mem/packet.hh" 43 44class CacheBlk; 45class MSHRQueue; 46 47/** 48 * Miss Status and handling Register. This class keeps all the information 49 * needed to handle a cache miss including a list of target requests. 50 * @sa \ref gem5MemorySystem "gem5 Memory System" 51 */ 52class MSHR : public Packet::SenderState, public Printable 53{ 54 55 public: 56 57 class Target { 58 public: 59 60 enum Source { 61 FromCPU, 62 FromSnoop, 63 FromPrefetcher 64 }; 65 66 Tick recvTime; //!< Time when request was received (for stats) 67 Tick readyTime; //!< Time when request is ready to be serviced 68 Counter order; //!< Global order (for memory consistency mgmt) 69 PacketPtr pkt; //!< Pending request packet. 70 Source source; //!< Did request come from cpu, memory, or prefetcher? 71 bool markedPending; //!< Did we mark upstream MSHR 72 //!< as downstreamPending? 73 74 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 75 Source _source, bool _markedPending) 76 : recvTime(curTick()), readyTime(_readyTime), order(_order), 77 pkt(_pkt), source(_source), markedPending(_markedPending) 78 {} 79 }; 80 81 class TargetList : public std::list<Target> { 82 /** Target list iterator. */ 83 typedef std::list<Target>::iterator Iterator; 84 typedef std::list<Target>::const_iterator ConstIterator; 85 86 public: 87 bool needsExclusive; 88 bool hasUpgrade; 89 90 TargetList(); 91 void resetFlags() { needsExclusive = hasUpgrade = false; } 92 bool isReset() { return !needsExclusive && !hasUpgrade; } 93 void add(PacketPtr pkt, Tick readyTime, Counter order, 94 Target::Source source, bool markPending); 95 void replaceUpgrades(); 96 void clearDownstreamPending(); 97 bool checkFunctional(PacketPtr pkt); 98 void print(std::ostream &os, int verbosity, 99 const std::string &prefix) const; 100 }; 101 102 /** A list of MSHRs. */ 103 typedef std::list<MSHR *> List; 104 /** MSHR list iterator. */ 105 typedef List::iterator Iterator; 106 /** MSHR list const_iterator. */ 107 typedef List::const_iterator ConstIterator; 108 109 /** Pointer to queue containing this MSHR. */ 110 MSHRQueue *queue; 111 112 /** Cycle when ready to issue */ 113 Tick readyTime; 114 115 /** Order number assigned by the miss queue. */ 116 Counter order; 117 118 /** Address of the request. */ 119 Addr addr; 120 121 /** Size of the request. */ 122 int size; 123 124 /** True if the request has been sent to the bus. */ 125 bool inService; 126 127 /** True if the request is just a simple forward from an upper level */ 128 bool isForward; 129 130 /** True if we need to get an exclusive copy of the block. */ 131 bool needsExclusive() const { return targets->needsExclusive; } 132 133 /** True if the request is uncacheable */ 134 bool _isUncacheable; 135 136 bool downstreamPending; 137 138 /** The pending* and post* flags are only valid if inService is 139 * true. Using the accessor functions lets us detect if these 140 * flags are accessed improperly. 141 */ 142 143 /** Will we have a dirty copy after this request? */ 144 bool pendingDirty; 145 bool isPendingDirty() const { 146 assert(inService); return pendingDirty; 147 } 148 149 /** Did we snoop an invalidate while waiting for data? */ 150 bool postInvalidate; 151 bool hasPostInvalidate() const { 152 assert(inService); return postInvalidate; 153 } 154 155 /** Did we snoop a read while waiting for data? */ 156 bool postDowngrade; 157 bool hasPostDowngrade() const { 158 assert(inService); return postDowngrade; 159 } 160 161 /** Thread number of the miss. */ 162 ThreadID threadNum; 163 /** The number of currently allocated targets. */ 164 unsigned short ntargets; 165 166 167 /** Data buffer (if needed). Currently used only for pending 168 * upgrade handling. */ 169 uint8_t *data; 170 171 /** 172 * Pointer to this MSHR on the ready list. 173 * @sa MissQueue, MSHRQueue::readyList 174 */ 175 Iterator readyIter; 176 177 /** 178 * Pointer to this MSHR on the allocated list. 179 * @sa MissQueue, MSHRQueue::allocatedList 180 */ 181 Iterator allocIter; 182 183private: 184 /** List of all requests that match the address */ 185 TargetList *targets; 186 187 TargetList *deferredTargets; 188 189public: 190 191 bool isUncacheable() { return _isUncacheable; } 192 193 /** 194 * Allocate a miss to this MSHR. 195 * @param cmd The requesting command. 196 * @param addr The address of the miss. 197 * @param asid The address space id of the miss. 198 * @param size The number of bytes to request. 199 * @param pkt The original miss. 200 */ 201 void allocate(Addr addr, int size, PacketPtr pkt, 202 Tick when, Counter _order); 203 204 bool markInService(PacketPtr pkt); 205 206 void clearDownstreamPending(); 207 208 /** 209 * Mark this MSHR as free. 210 */ 211 void deallocate(); 212 213 /** 214 * Add a request to the list of targets. 215 * @param target The target. 216 */ 217 void allocateTarget(PacketPtr target, Tick when, Counter order); 218 bool handleSnoop(PacketPtr target, Counter order); 219 220 /** A simple constructor. */ 221 MSHR(); 222 /** A simple destructor. */ 223 ~MSHR(); 224 225 /** 226 * Returns the current number of allocated targets. 227 * @return The current number of allocated targets. 228 */ 229 int getNumTargets() const { return ntargets; } 230 231 /** 232 * Returns a pointer to the target list. 233 * @return a pointer to the target list. 234 */ 235 TargetList *getTargetList() { return targets; } 236 237 /** 238 * Returns true if there are targets left. 239 * @return true if there are targets 240 */ 241 bool hasTargets() const { return !targets->empty(); } 242 243 /** 244 * Returns a reference to the first target. 245 * @return A pointer to the first target. 246 */ 247 Target *getTarget() const 248 { 249 assert(hasTargets()); 250 return &targets->front(); 251 } 252 253 /** 254 * Pop first target. 255 */ 256 void popTarget() 257 { 258 --ntargets; 259 targets->pop_front(); 260 } 261 262 bool isForwardNoResponse() const 263 { 264 if (getNumTargets() != 1) 265 return false; 266 Target *tgt = getTarget(); 267 return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse(); 268 } 269 270 bool promoteDeferredTargets(); 271 272 void handleFill(Packet *pkt, CacheBlk *blk); 273 274 bool checkFunctional(PacketPtr pkt); 275 276 /** 277 * Prints the contents of this MSHR for debugging. 278 */ 279 void print(std::ostream &os, 280 int verbosity = 0, 281 const std::string &prefix = "") const; 282}; 283 284#endif //__MSHR_HH__ 285