mshr.hh revision 5314
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 */ 30 31/** 32 * @file 33 * Miss Status and Handling Register (MSHR) declaration. 34 */ 35 36#ifndef __MSHR_HH__ 37#define __MSHR_HH__ 38 39#include <list> 40 41#include "base/printable.hh" 42#include "mem/packet.hh" 43 44class CacheBlk; 45class MSHRQueue; 46 47/** 48 * Miss Status and handling Register. This class keeps all the information 49 * needed to handle a cache miss including a list of target requests. 50 */ 51class MSHR : public Packet::SenderState, public Printable 52{ 53 54 public: 55 56 class Target { 57 public: 58 Tick recvTime; //!< Time when request was received (for stats) 59 Tick readyTime; //!< Time when request is ready to be serviced 60 Counter order; //!< Global order (for memory consistency mgmt) 61 PacketPtr pkt; //!< Pending request packet. 62 bool cpuSide; //!< Did request come from cpu side or mem side? 63 64 bool isCpuSide() const { return cpuSide; } 65 66 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide) 67 : recvTime(curTick), readyTime(_readyTime), order(_order), 68 pkt(_pkt), cpuSide(_cpuSide) 69 {} 70 }; 71 72 class TargetList : public std::list<Target> { 73 /** Target list iterator. */ 74 typedef std::list<Target>::iterator Iterator; 75 typedef std::list<Target>::const_iterator ConstIterator; 76 77 public: 78 bool needsExclusive; 79 bool hasUpgrade; 80 81 TargetList(); 82 void resetFlags() { needsExclusive = hasUpgrade = false; } 83 bool isReset() { return !needsExclusive && !hasUpgrade; } 84 void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide); 85 void replaceUpgrades(); 86 void clearDownstreamPending(); 87 bool checkFunctional(PacketPtr pkt); 88 void print(std::ostream &os, int verbosity, 89 const std::string &prefix) const; 90 }; 91 92 /** A list of MSHRs. */ 93 typedef std::list<MSHR *> List; 94 /** MSHR list iterator. */ 95 typedef List::iterator Iterator; 96 /** MSHR list const_iterator. */ 97 typedef List::const_iterator ConstIterator; 98 99 /** Pointer to queue containing this MSHR. */ 100 MSHRQueue *queue; 101 102 /** Cycle when ready to issue */ 103 Tick readyTime; 104 105 /** Order number assigned by the miss queue. */ 106 Counter order; 107 108 /** Address of the request. */ 109 Addr addr; 110 111 /** Size of the request. */ 112 int size; 113 114 /** True if the request has been sent to the bus. */ 115 bool inService; 116 117 /** True if we will be putting the returned block in the cache */ 118 bool isCacheFill; 119 120 /** True if we need to get an exclusive copy of the block. */ 121 bool needsExclusive() const { return targets->needsExclusive; } 122 123 /** True if the request is uncacheable */ 124 bool _isUncacheable; 125 126 bool downstreamPending; 127 128 bool pendingInvalidate; 129 bool pendingShared; 130 131 /** Thread number of the miss. */ 132 short threadNum; 133 /** The number of currently allocated targets. */ 134 short ntargets; 135 136 137 /** Data buffer (if needed). Currently used only for pending 138 * upgrade handling. */ 139 uint8_t *data; 140 141 /** 142 * Pointer to this MSHR on the ready list. 143 * @sa MissQueue, MSHRQueue::readyList 144 */ 145 Iterator readyIter; 146 147 /** 148 * Pointer to this MSHR on the allocated list. 149 * @sa MissQueue, MSHRQueue::allocatedList 150 */ 151 Iterator allocIter; 152 153private: 154 /** List of all requests that match the address */ 155 TargetList *targets; 156 157 TargetList *deferredTargets; 158 159public: 160 161 bool isUncacheable() { return _isUncacheable; } 162 163 /** 164 * Allocate a miss to this MSHR. 165 * @param cmd The requesting command. 166 * @param addr The address of the miss. 167 * @param asid The address space id of the miss. 168 * @param size The number of bytes to request. 169 * @param pkt The original miss. 170 */ 171 void allocate(Addr addr, int size, PacketPtr pkt, 172 Tick when, Counter _order); 173 174 bool markInService(); 175 176 /** 177 * Mark this MSHR as free. 178 */ 179 void deallocate(); 180 181 /** 182 * Add a request to the list of targets. 183 * @param target The target. 184 */ 185 void allocateTarget(PacketPtr target, Tick when, Counter order); 186 bool handleSnoop(PacketPtr target, Counter order); 187 188 /** A simple constructor. */ 189 MSHR(); 190 /** A simple destructor. */ 191 ~MSHR(); 192 193 /** 194 * Returns the current number of allocated targets. 195 * @return The current number of allocated targets. 196 */ 197 int getNumTargets() { return ntargets; } 198 199 /** 200 * Returns a pointer to the target list. 201 * @return a pointer to the target list. 202 */ 203 TargetList *getTargetList() { return targets; } 204 205 /** 206 * Returns true if there are targets left. 207 * @return true if there are targets 208 */ 209 bool hasTargets() { return !targets->empty(); } 210 211 /** 212 * Returns a reference to the first target. 213 * @return A pointer to the first target. 214 */ 215 Target *getTarget() { assert(hasTargets()); return &targets->front(); } 216 217 /** 218 * Pop first target. 219 */ 220 void popTarget() 221 { 222 --ntargets; 223 targets->pop_front(); 224 } 225 226 bool isSimpleForward() 227 { 228 if (getNumTargets() != 1) 229 return false; 230 Target *tgt = getTarget(); 231 return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 232 } 233 234 bool promoteDeferredTargets(); 235 236 void handleFill(Packet *pkt, CacheBlk *blk); 237 238 bool checkFunctional(PacketPtr pkt); 239 240 /** 241 * Prints the contents of this MSHR for debugging. 242 */ 243 void print(std::ostream &os, 244 int verbosity = 0, 245 const std::string &prefix = "") const; 246}; 247 248#endif //__MSHR_HH__ 249