mshr.hh revision 4626
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 */ 30 31/** 32 * @file 33 * Miss Status and Handling Register (MSHR) declaration. 34 */ 35 36#ifndef __MSHR_HH__ 37#define __MSHR_HH__ 38 39#include <list> 40 41#include "mem/packet.hh" 42 43class CacheBlk; 44class MSHRQueue; 45 46/** 47 * Miss Status and handling Register. This class keeps all the information 48 * needed to handle a cache miss including a list of target requests. 49 */ 50class MSHR : public Packet::SenderState 51{ 52 53 public: 54 55 class Target { 56 public: 57 Tick time; //!< Time when request was received (for stats) 58 PacketPtr pkt; //!< Pending request packet. 59 bool cpuSide; //!< Did request come from cpu side or mem side? 60 61 bool isCpuSide() { return cpuSide; } 62 63 Target(PacketPtr _pkt, bool _cpuSide, Tick _time = curTick) 64 : time(_time), pkt(_pkt), cpuSide(_cpuSide) 65 {} 66 }; 67 68 /** Defines the Data structure of the MSHR targetlist. */ 69 typedef std::list<Target> TargetList; 70 /** Target list iterator. */ 71 typedef std::list<Target>::iterator TargetListIterator; 72 /** A list of MSHRs. */ 73 typedef std::list<MSHR *> List; 74 /** MSHR list iterator. */ 75 typedef List::iterator Iterator; 76 /** MSHR list const_iterator. */ 77 typedef List::const_iterator ConstIterator; 78 79 /** Pointer to queue containing this MSHR. */ 80 MSHRQueue *queue; 81 82 /** Address of the request. */ 83 Addr addr; 84 85 /** Size of the request. */ 86 int size; 87 88 /** Data associated with the request (if a write). */ 89 uint8_t *writeData; 90 91 /** True if the request has been sent to the bus. */ 92 bool inService; 93 94 /** True if we will be putting the returned block in the cache */ 95 bool isCacheFill; 96 /** True if we need to get an exclusive copy of the block. */ 97 bool needsExclusive; 98 /** True if the request is uncacheable */ 99 bool _isUncacheable; 100 101 /** True if the request that has been sent to the bus is for en 102 * exclusive copy. */ 103 bool inServiceForExclusive; 104 /** Thread number of the miss. */ 105 short threadNum; 106 /** The number of currently allocated targets. */ 107 short ntargets; 108 /** Order number of assigned by the miss queue. */ 109 uint64_t order; 110 111 /** 112 * Pointer to this MSHR on the ready list. 113 * @sa MissQueue, MSHRQueue::readyList 114 */ 115 Iterator readyIter; 116 117 /** 118 * Pointer to this MSHR on the allocated list. 119 * @sa MissQueue, MSHRQueue::allocatedList 120 */ 121 Iterator allocIter; 122 123private: 124 /** List of all requests that match the address */ 125 TargetList targets; 126 127public: 128 129 bool isUncacheable() { return _isUncacheable; } 130 131 /** 132 * Allocate a miss to this MSHR. 133 * @param cmd The requesting command. 134 * @param addr The address of the miss. 135 * @param asid The address space id of the miss. 136 * @param size The number of bytes to request. 137 * @param pkt The original miss. 138 */ 139 void allocate(Addr addr, int size, PacketPtr pkt, bool isFill); 140 141 /** 142 * Allocate this MSHR as a buffer for the given request. 143 * @param target The memory request to buffer. 144 */ 145 void allocateAsBuffer(PacketPtr target); 146 147 /** 148 * Mark this MSHR as free. 149 */ 150 void deallocate(); 151 152 /** 153 * Add a request to the list of targets. 154 * @param target The target. 155 */ 156 void allocateTarget(PacketPtr target, bool cpuSide); 157 158 /** A simple constructor. */ 159 MSHR(); 160 /** A simple destructor. */ 161 ~MSHR(); 162 163 /** 164 * Returns the current number of allocated targets. 165 * @return The current number of allocated targets. 166 */ 167 int getNumTargets() 168 { 169 return ntargets; 170 } 171 172 /** 173 * Returns a pointer to the target list. 174 * @return a pointer to the target list. 175 */ 176 TargetList* getTargetList() 177 { 178 return &targets; 179 } 180 181 /** 182 * Returns a reference to the first target. 183 * @return A pointer to the first target. 184 */ 185 Target *getTarget() 186 { 187 return &targets.front(); 188 } 189 190 /** 191 * Pop first target. 192 */ 193 void popTarget() 194 { 195 --ntargets; 196 targets.pop_front(); 197 } 198 199 /** 200 * Returns true if there are targets left. 201 * @return true if there are targets 202 */ 203 bool hasTargets() 204 { 205 return !targets.empty(); 206 } 207 208 /** 209 * Prints the contents of this MSHR to stderr. 210 */ 211 void dump(); 212}; 213 214#endif //__MSHR_HH__ 215