mshr.hh revision 2810
17119Sgblack@eecs.umich.edu/* 27119Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 310183SCurtis.Dunham@arm.com * All rights reserved. 47119Sgblack@eecs.umich.edu * 57119Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67119Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77119Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87119Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97119Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107119Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117119Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127119Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137119Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147119Sgblack@eecs.umich.edu * this software without specific prior written permission. 157119Sgblack@eecs.umich.edu * 167119Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177119Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187119Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197119Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207119Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217119Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227119Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237119Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247119Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257119Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267119Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277119Sgblack@eecs.umich.edu * 287119Sgblack@eecs.umich.edu * Authors: Erik Hallnor 297119Sgblack@eecs.umich.edu */ 307119Sgblack@eecs.umich.edu 317119Sgblack@eecs.umich.edu/** 327119Sgblack@eecs.umich.edu * @file 337119Sgblack@eecs.umich.edu * Miss Status and Handling Register (MSHR) declaration. 347119Sgblack@eecs.umich.edu */ 357119Sgblack@eecs.umich.edu 367119Sgblack@eecs.umich.edu#ifndef __MSHR_HH__ 377119Sgblack@eecs.umich.edu#define __MSHR_HH__ 387119Sgblack@eecs.umich.edu 397119Sgblack@eecs.umich.edu#include "mem/packet.hh" 4010037SARM gem5 Developers#include <list> 4110037SARM gem5 Developers#include <deque> 4210037SARM gem5 Developers 437119Sgblack@eecs.umich.educlass MSHR; 447119Sgblack@eecs.umich.edu 457119Sgblack@eecs.umich.edu/** 467119Sgblack@eecs.umich.edu * Miss Status and handling Register. This class keeps all the information 477119Sgblack@eecs.umich.edu * needed to handle a cache miss including a list of target requests. 487120Sgblack@eecs.umich.edu */ 4910037SARM gem5 Developersclass MSHR { 5010037SARM gem5 Developers public: 5110037SARM gem5 Developers /** Defines the Data structure of the MSHR targetlist. */ 527199Sgblack@eecs.umich.edu typedef std::list<Packet *> TargetList; 537199Sgblack@eecs.umich.edu /** Target list iterator. */ 5410037SARM gem5 Developers typedef std::list<Packet *>::iterator TargetListIterator; 5510037SARM gem5 Developers /** A list of MSHRs. */ 5610197SCurtis.Dunham@arm.com typedef std::list<MSHR *> List; 5710197SCurtis.Dunham@arm.com /** MSHR list iterator. */ 5810197SCurtis.Dunham@arm.com typedef List::iterator Iterator; 5910037SARM gem5 Developers /** MSHR list const_iterator. */ 6010037SARM gem5 Developers typedef List::const_iterator ConstIterator; 617199Sgblack@eecs.umich.edu 627120Sgblack@eecs.umich.edu /** Address of the miss. */ 637120Sgblack@eecs.umich.edu Addr addr; 647134Sgblack@eecs.umich.edu /** Adress space id of the miss. */ 657205Sgblack@eecs.umich.edu short asid; 667205Sgblack@eecs.umich.edu /** True if the request has been sent to the bus. */ 677205Sgblack@eecs.umich.edu bool inService; 687134Sgblack@eecs.umich.edu /** Thread number of the miss. */ 697134Sgblack@eecs.umich.edu int threadNum; 707138Sgblack@eecs.umich.edu /** The request that is forwarded to the next level of the hierarchy. */ 7110197SCurtis.Dunham@arm.com Packet * pkt; 7210197SCurtis.Dunham@arm.com /** The number of currently allocated targets. */ 737138Sgblack@eecs.umich.edu short ntargets; 747138Sgblack@eecs.umich.edu /** The original requesting command. */ 757151Sgblack@eecs.umich.edu Packet::Command originalCmd; 7610037SARM gem5 Developers /** Order number of assigned by the miss queue. */ 7710037SARM gem5 Developers uint64_t order; 7810037SARM gem5 Developers 797151Sgblack@eecs.umich.edu /** 807151Sgblack@eecs.umich.edu * Pointer to this MSHR on the ready list. 8110037SARM gem5 Developers * @sa MissQueue, MSHRQueue::readyList 827160Sgblack@eecs.umich.edu */ 837160Sgblack@eecs.umich.edu Iterator readyIter; 847160Sgblack@eecs.umich.edu /** 857318Sgblack@eecs.umich.edu * Pointer to this MSHR on the allocated list. 867318Sgblack@eecs.umich.edu * @sa MissQueue, MSHRQueue::allocatedList 877318Sgblack@eecs.umich.edu */ 887322Sgblack@eecs.umich.edu Iterator allocIter; 897639Sgblack@eecs.umich.edu 907322Sgblack@eecs.umich.eduprivate: 9110037SARM gem5 Developers /** List of all requests that match the address */ 927639Sgblack@eecs.umich.edu TargetList targets; 9310197SCurtis.Dunham@arm.com 9410197SCurtis.Dunham@arm.compublic: 957639Sgblack@eecs.umich.edu /** 967639Sgblack@eecs.umich.edu * Allocate a miss to this MSHR. 977732SAli.Saidi@ARM.com * @param cmd The requesting command. 9810037SARM gem5 Developers * @param addr The address of the miss. 9910037SARM gem5 Developers * @param asid The address space id of the miss. 10010197SCurtis.Dunham@arm.com * @param size The number of bytes to request. 10110037SARM gem5 Developers * @param req The original miss. 10210037SARM gem5 Developers */ 10310197SCurtis.Dunham@arm.com void allocate(Packet::Command cmd, Addr addr, int asid, int size, 1047732SAli.Saidi@ARM.com Packet * &pkt); 105 106 /** 107 * Allocate this MSHR as a buffer for the given request. 108 * @param target The memory request to buffer. 109 */ 110 void allocateAsBuffer(Packet * &target); 111 112 /** 113 * Mark this MSHR as free. 114 */ 115 void deallocate(); 116 117 /** 118 * Add a request to the list of targets. 119 * @param target The target. 120 */ 121 void allocateTarget(Packet * &target); 122 123 /** A simple constructor. */ 124 MSHR(); 125 /** A simple destructor. */ 126 ~MSHR(); 127 128 /** 129 * Returns the current number of allocated targets. 130 * @return The current number of allocated targets. 131 */ 132 int getNumTargets() 133 { 134 return(ntargets); 135 } 136 137 /** 138 * Returns a pointer to the target list. 139 * @return a pointer to the target list. 140 */ 141 TargetList* getTargetList() 142 { 143 return &targets; 144 } 145 146 /** 147 * Returns a reference to the first target. 148 * @return A pointer to the first target. 149 */ 150 Packet * getTarget() 151 { 152 return targets.front(); 153 } 154 155 /** 156 * Pop first target. 157 */ 158 void popTarget() 159 { 160 --ntargets; 161 targets.pop_front(); 162 } 163 164 /** 165 * Returns true if there are targets left. 166 * @return true if there are targets 167 */ 168 bool hasTargets() 169 { 170 return !targets.empty(); 171 } 172 173 /** 174 * Prints the contents of this MSHR to stderr. 175 */ 176 void dump(); 177}; 178 179#endif //__MSHR_HH__ 180