mshr.hh revision 11278:18411ccc4f3c 
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <list>
52
53#include "base/printable.hh"
54#include "mem/packet.hh"
55
56class CacheBlk;
57class MSHRQueue;
58
59/**
60 * Miss Status and handling Register. This class keeps all the information
61 * needed to handle a cache miss including a list of target requests.
62 * @sa  \ref gem5MemorySystem "gem5 Memory System"
63 */
64class MSHR : public Packet::SenderState, public Printable
65{
66
67    /**
68     * Consider the MSHRQueue a friend to avoid making everything public
69     */
70    friend class MSHRQueue;
71
72  private:
73
74    /** Cycle when ready to issue */
75    Tick readyTime;
76
77    /** True if the request is uncacheable */
78    bool _isUncacheable;
79
80    /** Flag set by downstream caches */
81    bool downstreamPending;
82
83    /** Will we have a dirty copy after this request? */
84    bool pendingDirty;
85
86    /** Did we snoop an invalidate while waiting for data? */
87    bool postInvalidate;
88
89    /** Did we snoop a read while waiting for data? */
90    bool postDowngrade;
91
92  public:
93
94    class Target {
95      public:
96
97        enum Source {
98            FromCPU,
99            FromSnoop,
100            FromPrefetcher
101        };
102
103        const Tick recvTime;  //!< Time when request was received (for stats)
104        const Tick readyTime; //!< Time when request is ready to be serviced
105        const Counter order;  //!< Global order (for memory consistency mgmt)
106        const PacketPtr pkt;  //!< Pending request packet.
107        const Source source;  //!< Request from cpu, memory, or prefetcher?
108        const bool markedPending; //!< Did we mark upstream MSHR
109                                  //!< as downstreamPending?
110
111        Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
112               Source _source, bool _markedPending)
113            : recvTime(curTick()), readyTime(_readyTime), order(_order),
114              pkt(_pkt), source(_source), markedPending(_markedPending)
115        {}
116    };
117
118    class TargetList : public std::list<Target> {
119
120      public:
121        bool needsExclusive;
122        bool hasUpgrade;
123
124        TargetList();
125        void resetFlags() { needsExclusive = hasUpgrade = false; }
126        bool isReset() const { return !needsExclusive && !hasUpgrade; }
127        void add(PacketPtr pkt, Tick readyTime, Counter order,
128                 Target::Source source, bool markPending);
129        void replaceUpgrades();
130        void clearDownstreamPending();
131        bool checkFunctional(PacketPtr pkt);
132        void print(std::ostream &os, int verbosity,
133                   const std::string &prefix) const;
134    };
135
136    /** A list of MSHRs. */
137    typedef std::list<MSHR *> List;
138    /** MSHR list iterator. */
139    typedef List::iterator Iterator;
140    /** MSHR list const_iterator. */
141    typedef List::const_iterator ConstIterator;
142
143    /** Pointer to queue containing this MSHR. */
144    MSHRQueue *queue;
145
146    /** Order number assigned by the miss queue. */
147    Counter order;
148
149    /** Block aligned address of the MSHR. */
150    Addr blkAddr;
151
152    /** Block size of the cache. */
153    unsigned blkSize;
154
155    /** True if the request targets the secure memory space. */
156    bool isSecure;
157
158    /** True if the request has been sent to the bus. */
159    bool inService;
160
161    /** True if the request is just a simple forward from an upper level */
162    bool isForward;
163
164    /** Keep track of whether we should allocate on fill or not */
165    bool allocOnFill;
166
167    /** The pending* and post* flags are only valid if inService is
168     *  true.  Using the accessor functions lets us detect if these
169     *  flags are accessed improperly.
170     */
171
172    /** True if we need to get an exclusive copy of the block. */
173    bool needsExclusive() const { return targets.needsExclusive; }
174
175    bool isPendingDirty() const {
176        assert(inService); return pendingDirty;
177    }
178
179    bool hasPostInvalidate() const {
180        assert(inService); return postInvalidate;
181    }
182
183    bool hasPostDowngrade() const {
184        assert(inService); return postDowngrade;
185    }
186
187  private:
188
189    /** Data buffer (if needed).  Currently used only for pending
190     * upgrade handling. */
191    uint8_t *data;
192
193    /**
194     * Pointer to this MSHR on the ready list.
195     * @sa MissQueue, MSHRQueue::readyList
196     */
197    Iterator readyIter;
198
199    /**
200     * Pointer to this MSHR on the allocated list.
201     * @sa MissQueue, MSHRQueue::allocatedList
202     */
203    Iterator allocIter;
204
205    /** List of all requests that match the address */
206    TargetList targets;
207
208    TargetList deferredTargets;
209
210  public:
211
212    bool isUncacheable() const { return _isUncacheable; }
213
214    /**
215     * Allocate a miss to this MSHR.
216     * @param blk_addr The address of the block.
217     * @param blk_size The number of bytes to request.
218     * @param pkt The original miss.
219     * @param when_ready When should the MSHR be ready to act upon.
220     * @param _order The logical order of this MSHR
221     * @param alloc_on_fill Should the cache allocate a block on fill
222     */
223    void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
224                  Tick when_ready, Counter _order, bool alloc_on_fill);
225
226    bool markInService(bool pending_dirty_resp);
227
228    void clearDownstreamPending();
229
230    /**
231     * Mark this MSHR as free.
232     */
233    void deallocate();
234
235    /**
236     * Add a request to the list of targets.
237     * @param target The target.
238     */
239    void allocateTarget(PacketPtr target, Tick when, Counter order,
240                        bool alloc_on_fill);
241    bool handleSnoop(PacketPtr target, Counter order);
242
243    /** A simple constructor. */
244    MSHR();
245
246    /**
247     * Returns the current number of allocated targets.
248     * @return The current number of allocated targets.
249     */
250    int getNumTargets() const
251    { return targets.size() + deferredTargets.size(); }
252
253    /**
254     * Returns true if there are targets left.
255     * @return true if there are targets
256     */
257    bool hasTargets() const { return !targets.empty(); }
258
259    /**
260     * Returns a reference to the first target.
261     * @return A pointer to the first target.
262     */
263    Target *getTarget()
264    {
265        assert(hasTargets());
266        return &targets.front();
267    }
268
269    /**
270     * Pop first target.
271     */
272    void popTarget()
273    {
274        targets.pop_front();
275    }
276
277    bool isForwardNoResponse() const
278    {
279        if (getNumTargets() != 1)
280            return false;
281        const Target *tgt = &targets.front();
282        return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse();
283    }
284
285    bool promoteDeferredTargets();
286
287    void promoteExclusive();
288
289    bool checkFunctional(PacketPtr pkt);
290
291    /**
292     * Prints the contents of this MSHR for debugging.
293     */
294    void print(std::ostream &os,
295               int verbosity = 0,
296               const std::string &prefix = "") const;
297    /**
298     * A no-args wrapper of print(std::ostream...)  meant to be
299     * invoked from DPRINTFs avoiding string overheads in fast mode
300     *
301     * @return string with mshr fields + [deferred]targets
302     */
303    std::string print() const;
304};
305
306#endif // __MEM_CACHE_MSHR_HH__
307