mshr.hh revision 7823
12101SN/A/* 22084SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu * 285268Sksewell@umich.edu * Authors: Erik Hallnor 295268Sksewell@umich.edu */ 302754Sksewell@umich.edu 312084SN/A/** 322084SN/A * @file 332084SN/A * Miss Status and Handling Register (MSHR) declaration. 342084SN/A */ 352084SN/A 362084SN/A#ifndef __MSHR_HH__ 372084SN/A#define __MSHR_HH__ 382084SN/A 392084SN/A#include <list> 402101SN/A 412084SN/A#include "base/printable.hh" 422084SN/A#include "mem/packet.hh" 432084SN/A 442084SN/Aclass CacheBlk; 452084SN/Aclass MSHRQueue; 462084SN/A 472084SN/A/** 482101SN/A * Miss Status and handling Register. This class keeps all the information 492084SN/A * needed to handle a cache miss including a list of target requests. 502084SN/A */ 512084SN/Aclass MSHR : public Packet::SenderState, public Printable 522084SN/A{ 532084SN/A 542084SN/A public: 552084SN/A 562084SN/A class Target { 572084SN/A public: 582084SN/A 592084SN/A enum Source { 602084SN/A FromCPU, 612084SN/A FromSnoop, 622084SN/A FromPrefetcher 632084SN/A }; 642084SN/A 652084SN/A Tick recvTime; //!< Time when request was received (for stats) 662084SN/A Tick readyTime; //!< Time when request is ready to be serviced 672686Sksewell@umich.edu Counter order; //!< Global order (for memory consistency mgmt) 682084SN/A PacketPtr pkt; //!< Pending request packet. 692084SN/A Source source; //!< Did request come from cpu, memory, or prefetcher? 702084SN/A bool markedPending; //!< Did we mark upstream MSHR 712084SN/A //!< as downstreamPending? 722084SN/A 732101SN/A Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 742101SN/A Source _source, bool _markedPending) 752084SN/A : recvTime(curTick()), readyTime(_readyTime), order(_order), 762750Sksewell@umich.edu pkt(_pkt), source(_source), markedPending(_markedPending) 772750Sksewell@umich.edu {} 782084SN/A }; 792084SN/A 802084SN/A class TargetList : public std::list<Target> { 812084SN/A /** Target list iterator. */ 822084SN/A typedef std::list<Target>::iterator Iterator; 832084SN/A typedef std::list<Target>::const_iterator ConstIterator; 842084SN/A 852084SN/A public: 862084SN/A bool needsExclusive; 872239SN/A bool hasUpgrade; 882084SN/A 892084SN/A TargetList(); 902084SN/A void resetFlags() { needsExclusive = hasUpgrade = false; } 912750Sksewell@umich.edu bool isReset() { return !needsExclusive && !hasUpgrade; } 922750Sksewell@umich.edu void add(PacketPtr pkt, Tick readyTime, Counter order, 932750Sksewell@umich.edu Target::Source source, bool markPending); 942750Sksewell@umich.edu void replaceUpgrades(); 952750Sksewell@umich.edu void clearDownstreamPending(); 962750Sksewell@umich.edu bool checkFunctional(PacketPtr pkt); 972750Sksewell@umich.edu void print(std::ostream &os, int verbosity, 982750Sksewell@umich.edu const std::string &prefix) const; 992750Sksewell@umich.edu }; 1002750Sksewell@umich.edu 1012750Sksewell@umich.edu /** A list of MSHRs. */ 1022750Sksewell@umich.edu typedef std::list<MSHR *> List; 1032084SN/A /** MSHR list iterator. */ 1042084SN/A typedef List::iterator Iterator; 1052101SN/A /** MSHR list const_iterator. */ 1062750Sksewell@umich.edu typedef List::const_iterator ConstIterator; 1072750Sksewell@umich.edu 1082750Sksewell@umich.edu /** Pointer to queue containing this MSHR. */ 1092750Sksewell@umich.edu MSHRQueue *queue; 1102750Sksewell@umich.edu 1112750Sksewell@umich.edu /** Cycle when ready to issue */ 1122239SN/A Tick readyTime; 1132750Sksewell@umich.edu 1142750Sksewell@umich.edu /** Order number assigned by the miss queue. */ 1152750Sksewell@umich.edu Counter order; 1162750Sksewell@umich.edu 1172750Sksewell@umich.edu /** Address of the request. */ 1182750Sksewell@umich.edu Addr addr; 1192750Sksewell@umich.edu 1202750Sksewell@umich.edu /** Size of the request. */ 1212084SN/A int size; 1222084SN/A 1232084SN/A /** True if the request has been sent to the bus. */ 1242084SN/A bool inService; 1252084SN/A 1262084SN/A /** True if the request is just a simple forward from an upper level */ 1272084SN/A bool isForward; 1283951Sgblack@eecs.umich.edu 1292084SN/A /** True if we need to get an exclusive copy of the block. */ 1302084SN/A bool needsExclusive() const { return targets->needsExclusive; } 1312084SN/A 1322084SN/A /** True if the request is uncacheable */ 1332084SN/A bool _isUncacheable; 1342084SN/A 1352084SN/A bool downstreamPending; 1362470SN/A 1372686Sksewell@umich.edu /** The pending* and post* flags are only valid if inService is 1382470SN/A * true. Using the accessor functions lets us detect if these 1392470SN/A * flags are accessed improperly. 140 */ 141 142 /** Will we have a dirty copy after this request? */ 143 bool pendingDirty; 144 bool isPendingDirty() const { 145 assert(inService); return pendingDirty; 146 } 147 148 /** Did we snoop an invalidate while waiting for data? */ 149 bool postInvalidate; 150 bool hasPostInvalidate() const { 151 assert(inService); return postInvalidate; 152 } 153 154 /** Did we snoop a read while waiting for data? */ 155 bool postDowngrade; 156 bool hasPostDowngrade() const { 157 assert(inService); return postDowngrade; 158 } 159 160 /** Thread number of the miss. */ 161 ThreadID threadNum; 162 /** The number of currently allocated targets. */ 163 unsigned short ntargets; 164 165 166 /** Data buffer (if needed). Currently used only for pending 167 * upgrade handling. */ 168 uint8_t *data; 169 170 /** 171 * Pointer to this MSHR on the ready list. 172 * @sa MissQueue, MSHRQueue::readyList 173 */ 174 Iterator readyIter; 175 176 /** 177 * Pointer to this MSHR on the allocated list. 178 * @sa MissQueue, MSHRQueue::allocatedList 179 */ 180 Iterator allocIter; 181 182private: 183 /** List of all requests that match the address */ 184 TargetList *targets; 185 186 TargetList *deferredTargets; 187 188public: 189 190 bool isUncacheable() { return _isUncacheable; } 191 192 /** 193 * Allocate a miss to this MSHR. 194 * @param cmd The requesting command. 195 * @param addr The address of the miss. 196 * @param asid The address space id of the miss. 197 * @param size The number of bytes to request. 198 * @param pkt The original miss. 199 */ 200 void allocate(Addr addr, int size, PacketPtr pkt, 201 Tick when, Counter _order); 202 203 bool markInService(PacketPtr pkt); 204 205 void clearDownstreamPending(); 206 207 /** 208 * Mark this MSHR as free. 209 */ 210 void deallocate(); 211 212 /** 213 * Add a request to the list of targets. 214 * @param target The target. 215 */ 216 void allocateTarget(PacketPtr target, Tick when, Counter order); 217 bool handleSnoop(PacketPtr target, Counter order); 218 219 /** A simple constructor. */ 220 MSHR(); 221 /** A simple destructor. */ 222 ~MSHR(); 223 224 /** 225 * Returns the current number of allocated targets. 226 * @return The current number of allocated targets. 227 */ 228 int getNumTargets() const { return ntargets; } 229 230 /** 231 * Returns a pointer to the target list. 232 * @return a pointer to the target list. 233 */ 234 TargetList *getTargetList() { return targets; } 235 236 /** 237 * Returns true if there are targets left. 238 * @return true if there are targets 239 */ 240 bool hasTargets() const { return !targets->empty(); } 241 242 /** 243 * Returns a reference to the first target. 244 * @return A pointer to the first target. 245 */ 246 Target *getTarget() const 247 { 248 assert(hasTargets()); 249 return &targets->front(); 250 } 251 252 /** 253 * Pop first target. 254 */ 255 void popTarget() 256 { 257 --ntargets; 258 targets->pop_front(); 259 } 260 261 bool isForwardNoResponse() const 262 { 263 if (getNumTargets() != 1) 264 return false; 265 Target *tgt = getTarget(); 266 return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse(); 267 } 268 269 bool promoteDeferredTargets(); 270 271 void handleFill(Packet *pkt, CacheBlk *blk); 272 273 bool checkFunctional(PacketPtr pkt); 274 275 /** 276 * Prints the contents of this MSHR for debugging. 277 */ 278 void print(std::ostream &os, 279 int verbosity = 0, 280 const std::string &prefix = "") const; 281}; 282 283#endif //__MSHR_HH__ 284