mshr.hh revision 5730
12810SN/A/* 22810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Miss Status and Handling Register (MSHR) declaration. 342810SN/A */ 352810SN/A 362810SN/A#ifndef __MSHR_HH__ 372810SN/A#define __MSHR_HH__ 382810SN/A 394626SN/A#include <list> 404626SN/A 415314SN/A#include "base/printable.hh" 422810SN/A#include "mem/packet.hh" 432810SN/A 444626SN/Aclass CacheBlk; 454626SN/Aclass MSHRQueue; 462810SN/A 472810SN/A/** 482810SN/A * Miss Status and handling Register. This class keeps all the information 493374SN/A * needed to handle a cache miss including a list of target requests. 502810SN/A */ 515314SN/Aclass MSHR : public Packet::SenderState, public Printable 524626SN/A{ 534626SN/A 542810SN/A public: 554626SN/A 564626SN/A class Target { 574626SN/A public: 584871SN/A Tick recvTime; //!< Time when request was received (for stats) 594871SN/A Tick readyTime; //!< Time when request is ready to be serviced 604666SN/A Counter order; //!< Global order (for memory consistency mgmt) 614626SN/A PacketPtr pkt; //!< Pending request packet. 624626SN/A bool cpuSide; //!< Did request come from cpu side or mem side? 635318SN/A bool markedPending; //!< Did we mark upstream MSHR 645318SN/A //!< as downstreamPending? 654626SN/A 665314SN/A bool isCpuSide() const { return cpuSide; } 674626SN/A 685318SN/A Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 695318SN/A bool _cpuSide, bool _markedPending) 704871SN/A : recvTime(curTick), readyTime(_readyTime), order(_order), 715318SN/A pkt(_pkt), cpuSide(_cpuSide), markedPending(_markedPending) 724626SN/A {} 734626SN/A }; 744626SN/A 754903SN/A class TargetList : public std::list<Target> { 764903SN/A /** Target list iterator. */ 774903SN/A typedef std::list<Target>::iterator Iterator; 785314SN/A typedef std::list<Target>::const_iterator ConstIterator; 794903SN/A 804903SN/A public: 814903SN/A bool needsExclusive; 824903SN/A bool hasUpgrade; 834903SN/A 844903SN/A TargetList(); 854903SN/A void resetFlags() { needsExclusive = hasUpgrade = false; } 864903SN/A bool isReset() { return !needsExclusive && !hasUpgrade; } 875318SN/A void add(PacketPtr pkt, Tick readyTime, Counter order, 885318SN/A bool cpuSide, bool markPending); 894903SN/A void replaceUpgrades(); 904908SN/A void clearDownstreamPending(); 914920SN/A bool checkFunctional(PacketPtr pkt); 925314SN/A void print(std::ostream &os, int verbosity, 935314SN/A const std::string &prefix) const; 944903SN/A }; 954903SN/A 962810SN/A /** A list of MSHRs. */ 972810SN/A typedef std::list<MSHR *> List; 982810SN/A /** MSHR list iterator. */ 992810SN/A typedef List::iterator Iterator; 1002810SN/A /** MSHR list const_iterator. */ 1012810SN/A typedef List::const_iterator ConstIterator; 1022810SN/A 1034626SN/A /** Pointer to queue containing this MSHR. */ 1044626SN/A MSHRQueue *queue; 1054626SN/A 1064666SN/A /** Cycle when ready to issue */ 1074871SN/A Tick readyTime; 1084666SN/A 1094666SN/A /** Order number assigned by the miss queue. */ 1104666SN/A Counter order; 1114666SN/A 1124626SN/A /** Address of the request. */ 1132810SN/A Addr addr; 1144626SN/A 1154626SN/A /** Size of the request. */ 1164626SN/A int size; 1174626SN/A 1183374SN/A /** True if the request has been sent to the bus. */ 1192810SN/A bool inService; 1204626SN/A 1215730SSteve.Reinhardt@amd.com /** True if the request is just a simple forward from an upper level */ 1225730SSteve.Reinhardt@amd.com bool isForward; 1234903SN/A 1244626SN/A /** True if we need to get an exclusive copy of the block. */ 1255314SN/A bool needsExclusive() const { return targets->needsExclusive; } 1264665SN/A 1274626SN/A /** True if the request is uncacheable */ 1284626SN/A bool _isUncacheable; 1294626SN/A 1304908SN/A bool downstreamPending; 1314908SN/A 1324665SN/A bool pendingInvalidate; 1334670SN/A bool pendingShared; 1344665SN/A 1352810SN/A /** Thread number of the miss. */ 1364626SN/A short threadNum; 1372810SN/A /** The number of currently allocated targets. */ 1382810SN/A short ntargets; 1392810SN/A 1404668SN/A 1414668SN/A /** Data buffer (if needed). Currently used only for pending 1424668SN/A * upgrade handling. */ 1434668SN/A uint8_t *data; 1444668SN/A 1452810SN/A /** 1462810SN/A * Pointer to this MSHR on the ready list. 1472810SN/A * @sa MissQueue, MSHRQueue::readyList 1482810SN/A */ 1492810SN/A Iterator readyIter; 1504626SN/A 1512810SN/A /** 1522810SN/A * Pointer to this MSHR on the allocated list. 1532810SN/A * @sa MissQueue, MSHRQueue::allocatedList 1542810SN/A */ 1552810SN/A Iterator allocIter; 1562810SN/A 1572810SN/Aprivate: 1583374SN/A /** List of all requests that match the address */ 1594903SN/A TargetList *targets; 1602810SN/A 1614903SN/A TargetList *deferredTargets; 1624665SN/A 1632810SN/Apublic: 1644626SN/A 1654626SN/A bool isUncacheable() { return _isUncacheable; } 1664626SN/A 1672810SN/A /** 1682810SN/A * Allocate a miss to this MSHR. 1693374SN/A * @param cmd The requesting command. 1702810SN/A * @param addr The address of the miss. 1712810SN/A * @param asid The address space id of the miss. 1723374SN/A * @param size The number of bytes to request. 1732982SN/A * @param pkt The original miss. 1742810SN/A */ 1754666SN/A void allocate(Addr addr, int size, PacketPtr pkt, 1764666SN/A Tick when, Counter _order); 1772810SN/A 1784908SN/A bool markInService(); 1794908SN/A 1805318SN/A void clearDownstreamPending(); 1815318SN/A 1822810SN/A /** 1832810SN/A * Mark this MSHR as free. 1842810SN/A */ 1852810SN/A void deallocate(); 1862810SN/A 1872810SN/A /** 1883374SN/A * Add a request to the list of targets. 1892810SN/A * @param target The target. 1902810SN/A */ 1914666SN/A void allocateTarget(PacketPtr target, Tick when, Counter order); 1924902SN/A bool handleSnoop(PacketPtr target, Counter order); 1932810SN/A 1942810SN/A /** A simple constructor. */ 1952810SN/A MSHR(); 1962810SN/A /** A simple destructor. */ 1972810SN/A ~MSHR(); 1982810SN/A 1992810SN/A /** 2002810SN/A * Returns the current number of allocated targets. 2012810SN/A * @return The current number of allocated targets. 2022810SN/A */ 2035730SSteve.Reinhardt@amd.com int getNumTargets() const { return ntargets; } 2042810SN/A 2052810SN/A /** 2062810SN/A * Returns a pointer to the target list. 2072810SN/A * @return a pointer to the target list. 2082810SN/A */ 2094903SN/A TargetList *getTargetList() { return targets; } 2102810SN/A 2112810SN/A /** 2124899SN/A * Returns true if there are targets left. 2134899SN/A * @return true if there are targets 2144899SN/A */ 2155730SSteve.Reinhardt@amd.com bool hasTargets() const { return !targets->empty(); } 2164899SN/A 2174899SN/A /** 2182810SN/A * Returns a reference to the first target. 2192810SN/A * @return A pointer to the first target. 2202810SN/A */ 2215730SSteve.Reinhardt@amd.com Target *getTarget() const 2225730SSteve.Reinhardt@amd.com { 2235730SSteve.Reinhardt@amd.com assert(hasTargets()); 2245730SSteve.Reinhardt@amd.com return &targets->front(); 2255730SSteve.Reinhardt@amd.com } 2262810SN/A 2272810SN/A /** 2282810SN/A * Pop first target. 2292810SN/A */ 2302810SN/A void popTarget() 2312810SN/A { 2322810SN/A --ntargets; 2334903SN/A targets->pop_front(); 2342810SN/A } 2352810SN/A 2365730SSteve.Reinhardt@amd.com bool isForwardNoResponse() const 2372810SN/A { 2384630SN/A if (getNumTargets() != 1) 2394630SN/A return false; 2404630SN/A Target *tgt = getTarget(); 2414630SN/A return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 2422810SN/A } 2432810SN/A 2444665SN/A bool promoteDeferredTargets(); 2454665SN/A 2464671SN/A void handleFill(Packet *pkt, CacheBlk *blk); 2474668SN/A 2485314SN/A bool checkFunctional(PacketPtr pkt); 2494920SN/A 2502810SN/A /** 2515314SN/A * Prints the contents of this MSHR for debugging. 2522810SN/A */ 2535314SN/A void print(std::ostream &os, 2545314SN/A int verbosity = 0, 2555314SN/A const std::string &prefix = "") const; 2562810SN/A}; 2572810SN/A 2582810SN/A#endif //__MSHR_HH__ 259