mshr.hh revision 4920 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Miss Status and Handling Register (MSHR) declaration.
34 */
35
36#ifndef __MSHR_HH__
37#define __MSHR_HH__
38
39#include <list>
40
41#include "mem/packet.hh"
42
43class CacheBlk;
44class MSHRQueue;
45
46/**
47 * Miss Status and handling Register. This class keeps all the information
48 * needed to handle a cache miss including a list of target requests.
49 */
50class MSHR : public Packet::SenderState
51{
52
53  public:
54
55    class Target {
56      public:
57        Tick recvTime;  //!< Time when request was received (for stats)
58        Tick readyTime; //!< Time when request is ready to be serviced
59        Counter order;  //!< Global order (for memory consistency mgmt)
60        PacketPtr pkt;  //!< Pending request packet.
61        bool cpuSide;   //!< Did request come from cpu side or mem side?
62
63        bool isCpuSide() { return cpuSide; }
64
65        Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide)
66            : recvTime(curTick), readyTime(_readyTime), order(_order),
67              pkt(_pkt), cpuSide(_cpuSide)
68        {}
69    };
70
71    class TargetList : public std::list<Target> {
72        /** Target list iterator. */
73        typedef std::list<Target>::iterator Iterator;
74
75      public:
76        bool needsExclusive;
77        bool hasUpgrade;
78
79        TargetList();
80        void resetFlags() { needsExclusive = hasUpgrade = false; }
81        bool isReset()    { return !needsExclusive && !hasUpgrade; }
82        void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide);
83        void replaceUpgrades();
84        void clearDownstreamPending();
85        bool checkFunctional(PacketPtr pkt);
86    };
87
88    /** A list of MSHRs. */
89    typedef std::list<MSHR *> List;
90    /** MSHR list iterator. */
91    typedef List::iterator Iterator;
92    /** MSHR list const_iterator. */
93    typedef List::const_iterator ConstIterator;
94
95    /** Pointer to queue containing this MSHR. */
96    MSHRQueue *queue;
97
98    /** Cycle when ready to issue */
99    Tick readyTime;
100
101    /** Order number assigned by the miss queue. */
102    Counter order;
103
104    /** Address of the request. */
105    Addr addr;
106
107    /** Size of the request. */
108    int size;
109
110    /** True if the request has been sent to the bus. */
111    bool inService;
112
113    /** True if we will be putting the returned block in the cache */
114    bool isCacheFill;
115
116    /** True if we need to get an exclusive copy of the block. */
117    bool needsExclusive() { return targets->needsExclusive; }
118
119    /** True if the request is uncacheable */
120    bool _isUncacheable;
121
122    bool downstreamPending;
123
124    bool pendingInvalidate;
125    bool pendingShared;
126
127    /** Thread number of the miss. */
128    short threadNum;
129    /** The number of currently allocated targets. */
130    short ntargets;
131
132
133    /** Data buffer (if needed).  Currently used only for pending
134     * upgrade handling. */
135    uint8_t *data;
136
137    /**
138     * Pointer to this MSHR on the ready list.
139     * @sa MissQueue, MSHRQueue::readyList
140     */
141    Iterator readyIter;
142
143    /**
144     * Pointer to this MSHR on the allocated list.
145     * @sa MissQueue, MSHRQueue::allocatedList
146     */
147    Iterator allocIter;
148
149private:
150    /** List of all requests that match the address */
151    TargetList *targets;
152
153    TargetList *deferredTargets;
154
155public:
156
157    bool isUncacheable() { return _isUncacheable; }
158
159    /**
160     * Allocate a miss to this MSHR.
161     * @param cmd The requesting command.
162     * @param addr The address of the miss.
163     * @param asid The address space id of the miss.
164     * @param size The number of bytes to request.
165     * @param pkt  The original miss.
166     */
167    void allocate(Addr addr, int size, PacketPtr pkt,
168                  Tick when, Counter _order);
169
170    bool markInService();
171
172    /**
173     * Mark this MSHR as free.
174     */
175    void deallocate();
176
177    /**
178     * Add a request to the list of targets.
179     * @param target The target.
180     */
181    void allocateTarget(PacketPtr target, Tick when, Counter order);
182    bool handleSnoop(PacketPtr target, Counter order);
183
184    /** A simple constructor. */
185    MSHR();
186    /** A simple destructor. */
187    ~MSHR();
188
189    /**
190     * Returns the current number of allocated targets.
191     * @return The current number of allocated targets.
192     */
193    int getNumTargets() { return ntargets; }
194
195    /**
196     * Returns a pointer to the target list.
197     * @return a pointer to the target list.
198     */
199    TargetList *getTargetList() { return targets; }
200
201    /**
202     * Returns true if there are targets left.
203     * @return true if there are targets
204     */
205    bool hasTargets() { return !targets->empty(); }
206
207    /**
208     * Returns a reference to the first target.
209     * @return A pointer to the first target.
210     */
211    Target *getTarget() { assert(hasTargets());  return &targets->front(); }
212
213    /**
214     * Pop first target.
215     */
216    void popTarget()
217    {
218        --ntargets;
219        targets->pop_front();
220    }
221
222    bool isSimpleForward()
223    {
224        if (getNumTargets() != 1)
225            return false;
226        Target *tgt = getTarget();
227        return tgt->isCpuSide() && !tgt->pkt->needsResponse();
228    }
229
230    bool promoteDeferredTargets();
231
232    void handleFill(Packet *pkt, CacheBlk *blk);
233
234    bool checkFunctional(PacketPtr pkt) {
235        return (targets->checkFunctional(pkt) ||
236                deferredTargets->checkFunctional(pkt));
237    }
238
239    /**
240     * Prints the contents of this MSHR to stderr.
241     */
242    void dump();
243};
244
245#endif //__MSHR_HH__
246