mshr.hh revision 4908
16184SN/A/* 210330Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 38842Smrinmoy.ghosh@arm.com * All rights reserved. 48842Smrinmoy.ghosh@arm.com * 58842Smrinmoy.ghosh@arm.com * Redistribution and use in source and binary forms, with or without 68842Smrinmoy.ghosh@arm.com * modification, are permitted provided that the following conditions are 78842Smrinmoy.ghosh@arm.com * met: redistributions of source code must retain the above copyright 88842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer; 98842Smrinmoy.ghosh@arm.com * redistributions in binary form must reproduce the above copyright 108842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer in the 118842Smrinmoy.ghosh@arm.com * documentation and/or other materials provided with the distribution; 128842Smrinmoy.ghosh@arm.com * neither the name of the copyright holders nor the names of its 138842Smrinmoy.ghosh@arm.com * contributors may be used to endorse or promote products derived from 146184SN/A * this software without specific prior written permission. 156184SN/A * 166184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196184SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206184SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226184SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246184SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266184SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276184SN/A * 286184SN/A * Authors: Erik Hallnor 296184SN/A */ 306184SN/A 316184SN/A/** 326184SN/A * @file 336184SN/A * Miss Status and Handling Register (MSHR) declaration. 346184SN/A */ 356184SN/A 366184SN/A#ifndef __MSHR_HH__ 376184SN/A#define __MSHR_HH__ 386184SN/A 396184SN/A#include <list> 406184SN/A 416184SN/A#include "mem/packet.hh" 426184SN/A 4311793Sbrandon.potter@amd.comclass CacheBlk; 4411793Sbrandon.potter@amd.comclass MSHRQueue; 459360SE.Tomusk@sms.ed.ac.uk 466184SN/A/** 476184SN/A * Miss Status and handling Register. This class keeps all the information 4810785Sgope@wisc.edu * needed to handle a cache miss including a list of target requests. 499480Snilay@cs.wisc.edu */ 509691Satgutier@umich.educlass MSHR : public Packet::SenderState 519480Snilay@cs.wisc.edu{ 5213959Sodanrc@yahoo.com.br 539480Snilay@cs.wisc.edu public: 549691Satgutier@umich.edu 559480Snilay@cs.wisc.edu class Target { 569480Snilay@cs.wisc.edu public: 5713959Sodanrc@yahoo.com.br Tick recvTime; //!< Time when request was received (for stats) 5811434Smitch.hayenga@arm.com Tick readyTime; //!< Time when request is ready to be serviced 599691Satgutier@umich.edu Counter order; //!< Global order (for memory consistency mgmt) 609691Satgutier@umich.edu PacketPtr pkt; //!< Pending request packet. 619691Satgutier@umich.edu bool cpuSide; //!< Did request come from cpu side or mem side? 629691Satgutier@umich.edu 639691Satgutier@umich.edu bool isCpuSide() { return cpuSide; } 649480Snilay@cs.wisc.edu 6513959Sodanrc@yahoo.com.br Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide) 6613959Sodanrc@yahoo.com.br : recvTime(curTick), readyTime(_readyTime), order(_order), 676184SN/A pkt(_pkt), cpuSide(_cpuSide) 689691Satgutier@umich.edu {} 699691Satgutier@umich.edu }; 709691Satgutier@umich.edu 719691Satgutier@umich.edu class TargetList : public std::list<Target> { 729691Satgutier@umich.edu /** Target list iterator. */ 739691Satgutier@umich.edu typedef std::list<Target>::iterator Iterator; 749691Satgutier@umich.edu 756184SN/A public: 769360SE.Tomusk@sms.ed.ac.uk bool needsExclusive; 776184SN/A bool hasUpgrade; 786184SN/A 796184SN/A TargetList(); 806184SN/A void resetFlags() { needsExclusive = hasUpgrade = false; } 816184SN/A bool isReset() { return !needsExclusive && !hasUpgrade; } 826184SN/A void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide); 836184SN/A void replaceUpgrades(); 846184SN/A void clearDownstreamPending(); 856184SN/A }; 866184SN/A 876184SN/A /** A list of MSHRs. */ 889360SE.Tomusk@sms.ed.ac.uk typedef std::list<MSHR *> List; 899360SE.Tomusk@sms.ed.ac.uk /** MSHR list iterator. */ 909360SE.Tomusk@sms.ed.ac.uk typedef List::iterator Iterator; 916184SN/A /** MSHR list const_iterator. */ 926184SN/A typedef List::const_iterator ConstIterator; 936184SN/A 946184SN/A /** Pointer to queue containing this MSHR. */ 956184SN/A MSHRQueue *queue; 969360SE.Tomusk@sms.ed.ac.uk 979360SE.Tomusk@sms.ed.ac.uk /** Cycle when ready to issue */ 989360SE.Tomusk@sms.ed.ac.uk Tick readyTime; 999360SE.Tomusk@sms.ed.ac.uk 1009360SE.Tomusk@sms.ed.ac.uk /** Order number assigned by the miss queue. */ 1019360SE.Tomusk@sms.ed.ac.uk Counter order; 1029360SE.Tomusk@sms.ed.ac.uk 1039360SE.Tomusk@sms.ed.ac.uk /** Address of the request. */ 1049360SE.Tomusk@sms.ed.ac.uk Addr addr; 1059360SE.Tomusk@sms.ed.ac.uk 1069360SE.Tomusk@sms.ed.ac.uk /** Size of the request. */ 1079360SE.Tomusk@sms.ed.ac.uk int size; 1089360SE.Tomusk@sms.ed.ac.uk 1099360SE.Tomusk@sms.ed.ac.uk /** True if the request has been sent to the bus. */ 1109360SE.Tomusk@sms.ed.ac.uk bool inService; 1119360SE.Tomusk@sms.ed.ac.uk 1129360SE.Tomusk@sms.ed.ac.uk /** True if we will be putting the returned block in the cache */ 1139360SE.Tomusk@sms.ed.ac.uk bool isCacheFill; 1149360SE.Tomusk@sms.ed.ac.uk 1159360SE.Tomusk@sms.ed.ac.uk /** True if we need to get an exclusive copy of the block. */ 1169360SE.Tomusk@sms.ed.ac.uk bool needsExclusive() { return targets->needsExclusive; } 1179360SE.Tomusk@sms.ed.ac.uk 1189360SE.Tomusk@sms.ed.ac.uk /** True if the request is uncacheable */ 1199360SE.Tomusk@sms.ed.ac.uk bool _isUncacheable; 1209360SE.Tomusk@sms.ed.ac.uk 1216184SN/A bool downstreamPending; 1226184SN/A 1236184SN/A bool pendingInvalidate; 1246184SN/A bool pendingShared; 1256184SN/A 1266184SN/A /** Thread number of the miss. */ 1276184SN/A short threadNum; 1286184SN/A /** The number of currently allocated targets. */ 1296184SN/A short ntargets; 1306184SN/A 1316184SN/A 1326184SN/A /** Data buffer (if needed). Currently used only for pending 13311434Smitch.hayenga@arm.com * upgrade handling. */ 1346184SN/A uint8_t *data; 13511434Smitch.hayenga@arm.com 13611434Smitch.hayenga@arm.com /** 1376184SN/A * Pointer to this MSHR on the ready list. 1386184SN/A * @sa MissQueue, MSHRQueue::readyList 1396184SN/A */ 1406184SN/A Iterator readyIter; 14111434Smitch.hayenga@arm.com 1426184SN/A /** 14311434Smitch.hayenga@arm.com * Pointer to this MSHR on the allocated list. 14411434Smitch.hayenga@arm.com * @sa MissQueue, MSHRQueue::allocatedList 1456184SN/A */ 1466184SN/A Iterator allocIter; 1476184SN/A 1486184SN/Aprivate: 1496184SN/A /** List of all requests that match the address */ 1506184SN/A TargetList *targets; 1516184SN/A 1526184SN/A TargetList *deferredTargets; 1536184SN/A 1546184SN/Apublic: 1556184SN/A 1566184SN/A bool isUncacheable() { return _isUncacheable; } 1576184SN/A 1586184SN/A /** 1596184SN/A * Allocate a miss to this MSHR. 1606184SN/A * @param cmd The requesting command. 1616184SN/A * @param addr The address of the miss. 1626184SN/A * @param asid The address space id of the miss. 1638842Smrinmoy.ghosh@arm.com * @param size The number of bytes to request. 1648842Smrinmoy.ghosh@arm.com * @param pkt The original miss. 16511434Smitch.hayenga@arm.com */ 1668842Smrinmoy.ghosh@arm.com void allocate(Addr addr, int size, PacketPtr pkt, 1678842Smrinmoy.ghosh@arm.com Tick when, Counter _order); 1689360SE.Tomusk@sms.ed.ac.uk 16911434Smitch.hayenga@arm.com bool markInService(); 1708842Smrinmoy.ghosh@arm.com 1718842Smrinmoy.ghosh@arm.com /** 1729327Smrinmoy.ghosh@arm.com * Mark this MSHR as free. 1738842Smrinmoy.ghosh@arm.com */ 1748842Smrinmoy.ghosh@arm.com void deallocate(); 1756184SN/A 17611434Smitch.hayenga@arm.com /** 1776184SN/A * Add a request to the list of targets. 1786184SN/A * @param target The target. 1796184SN/A */ 1806184SN/A void allocateTarget(PacketPtr target, Tick when, Counter order); 1816184SN/A bool handleSnoop(PacketPtr target, Counter order); 1826184SN/A 1836184SN/A /** A simple constructor. */ 1846184SN/A MSHR(); 1856184SN/A /** A simple destructor. */ 1866184SN/A ~MSHR(); 1876184SN/A 1886184SN/A /** 18913959Sodanrc@yahoo.com.br * Returns the current number of allocated targets. 1906184SN/A * @return The current number of allocated targets. 1916184SN/A */ 19211434Smitch.hayenga@arm.com int getNumTargets() { return ntargets; } 19313959Sodanrc@yahoo.com.br 1946184SN/A /** 1956184SN/A * Returns a pointer to the target list. 19611434Smitch.hayenga@arm.com * @return a pointer to the target list. 19713959Sodanrc@yahoo.com.br */ 1986184SN/A TargetList *getTargetList() { return targets; } 1996184SN/A 2006184SN/A /** 20111434Smitch.hayenga@arm.com * Returns true if there are targets left. 2026184SN/A * @return true if there are targets 2036184SN/A */ 2046184SN/A bool hasTargets() { return !targets->empty(); } 20511098Slukefahr@umich.edu 2068842Smrinmoy.ghosh@arm.com /** 2076184SN/A * Returns a reference to the first target. 2086184SN/A * @return A pointer to the first target. 2099360SE.Tomusk@sms.ed.ac.uk */ 2106184SN/A Target *getTarget() { assert(hasTargets()); return &targets->front(); } 21111782Sarthur.perais@inria.fr 21211782Sarthur.perais@inria.fr /** 2136184SN/A * Pop first target. 2146184SN/A */ 21511434Smitch.hayenga@arm.com void popTarget() 2168842Smrinmoy.ghosh@arm.com { 2176184SN/A --ntargets; 2186184SN/A targets->pop_front(); 21911434Smitch.hayenga@arm.com } 2208842Smrinmoy.ghosh@arm.com 2216184SN/A bool isSimpleForward() 2226184SN/A { 2236184SN/A if (getNumTargets() != 1) 2246184SN/A return false; 22511434Smitch.hayenga@arm.com Target *tgt = getTarget(); 2268842Smrinmoy.ghosh@arm.com return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 2276184SN/A } 2286184SN/A 22911434Smitch.hayenga@arm.com bool promoteDeferredTargets(); 2308842Smrinmoy.ghosh@arm.com 2316184SN/A void handleFill(Packet *pkt, CacheBlk *blk); 2326184SN/A 2336184SN/A /** 2346184SN/A * Prints the contents of this MSHR to stderr. 2356184SN/A */ 2366184SN/A void dump(); 23711434Smitch.hayenga@arm.com}; 2386184SN/A 2396184SN/A#endif //__MSHR_HH__ 2406184SN/A