mshr.hh revision 4903
112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 312641Sgiacomo.travaglini@arm.com * All rights reserved. 412641Sgiacomo.travaglini@arm.com * 512641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 612641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 712641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 812641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 912641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1012641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1112641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1212641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1312641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1412641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1512641Sgiacomo.travaglini@arm.com * 1612641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712641Sgiacomo.travaglini@arm.com * 2812641Sgiacomo.travaglini@arm.com * Authors: Erik Hallnor 2912641Sgiacomo.travaglini@arm.com */ 3012641Sgiacomo.travaglini@arm.com 3112641Sgiacomo.travaglini@arm.com/** 3212641Sgiacomo.travaglini@arm.com * @file 3312641Sgiacomo.travaglini@arm.com * Miss Status and Handling Register (MSHR) declaration. 3412641Sgiacomo.travaglini@arm.com */ 3512641Sgiacomo.travaglini@arm.com 3612641Sgiacomo.travaglini@arm.com#ifndef __MSHR_HH__ 3712641Sgiacomo.travaglini@arm.com#define __MSHR_HH__ 3812641Sgiacomo.travaglini@arm.com 3912641Sgiacomo.travaglini@arm.com#include <list> 4012641Sgiacomo.travaglini@arm.com 4112641Sgiacomo.travaglini@arm.com#include "mem/packet.hh" 4212641Sgiacomo.travaglini@arm.com 4312641Sgiacomo.travaglini@arm.comclass CacheBlk; 4412641Sgiacomo.travaglini@arm.comclass MSHRQueue; 4512641Sgiacomo.travaglini@arm.com 4612641Sgiacomo.travaglini@arm.com/** 4712641Sgiacomo.travaglini@arm.com * Miss Status and handling Register. This class keeps all the information 4812641Sgiacomo.travaglini@arm.com * needed to handle a cache miss including a list of target requests. 4912641Sgiacomo.travaglini@arm.com */ 5012641Sgiacomo.travaglini@arm.comclass MSHR : public Packet::SenderState 5112641Sgiacomo.travaglini@arm.com{ 5212641Sgiacomo.travaglini@arm.com 5312641Sgiacomo.travaglini@arm.com public: 5412641Sgiacomo.travaglini@arm.com 5512641Sgiacomo.travaglini@arm.com class Target { 5612641Sgiacomo.travaglini@arm.com public: 5712641Sgiacomo.travaglini@arm.com Tick recvTime; //!< Time when request was received (for stats) 5812641Sgiacomo.travaglini@arm.com Tick readyTime; //!< Time when request is ready to be serviced 5912641Sgiacomo.travaglini@arm.com Counter order; //!< Global order (for memory consistency mgmt) 6012641Sgiacomo.travaglini@arm.com PacketPtr pkt; //!< Pending request packet. 6112641Sgiacomo.travaglini@arm.com bool cpuSide; //!< Did request come from cpu side or mem side? 6212641Sgiacomo.travaglini@arm.com 6312641Sgiacomo.travaglini@arm.com bool isCpuSide() { return cpuSide; } 6412641Sgiacomo.travaglini@arm.com 6512641Sgiacomo.travaglini@arm.com Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide) 6612641Sgiacomo.travaglini@arm.com : recvTime(curTick), readyTime(_readyTime), order(_order), 6712641Sgiacomo.travaglini@arm.com pkt(_pkt), cpuSide(_cpuSide) 6812641Sgiacomo.travaglini@arm.com {} 6912641Sgiacomo.travaglini@arm.com }; 7012641Sgiacomo.travaglini@arm.com 7112641Sgiacomo.travaglini@arm.com class TargetList : public std::list<Target> { 7212641Sgiacomo.travaglini@arm.com /** Target list iterator. */ 7312641Sgiacomo.travaglini@arm.com typedef std::list<Target>::iterator Iterator; 7412641Sgiacomo.travaglini@arm.com 7512641Sgiacomo.travaglini@arm.com public: 7612641Sgiacomo.travaglini@arm.com bool needsExclusive; 7712641Sgiacomo.travaglini@arm.com bool hasUpgrade; 7812641Sgiacomo.travaglini@arm.com 7912641Sgiacomo.travaglini@arm.com TargetList(); 8012641Sgiacomo.travaglini@arm.com void resetFlags() { needsExclusive = hasUpgrade = false; } 8112641Sgiacomo.travaglini@arm.com bool isReset() { return !needsExclusive && !hasUpgrade; } 8212641Sgiacomo.travaglini@arm.com void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide); 8312641Sgiacomo.travaglini@arm.com void replaceUpgrades(); 8412641Sgiacomo.travaglini@arm.com }; 8512641Sgiacomo.travaglini@arm.com 8612641Sgiacomo.travaglini@arm.com /** A list of MSHRs. */ 8712641Sgiacomo.travaglini@arm.com typedef std::list<MSHR *> List; 8812641Sgiacomo.travaglini@arm.com /** MSHR list iterator. */ 8912641Sgiacomo.travaglini@arm.com typedef List::iterator Iterator; 9012641Sgiacomo.travaglini@arm.com /** MSHR list const_iterator. */ 9112641Sgiacomo.travaglini@arm.com typedef List::const_iterator ConstIterator; 9212641Sgiacomo.travaglini@arm.com 9312641Sgiacomo.travaglini@arm.com /** Pointer to queue containing this MSHR. */ 9412641Sgiacomo.travaglini@arm.com MSHRQueue *queue; 9512641Sgiacomo.travaglini@arm.com 9612641Sgiacomo.travaglini@arm.com /** Cycle when ready to issue */ 9712641Sgiacomo.travaglini@arm.com Tick readyTime; 9812641Sgiacomo.travaglini@arm.com 9912641Sgiacomo.travaglini@arm.com /** Order number assigned by the miss queue. */ 10012641Sgiacomo.travaglini@arm.com Counter order; 10112641Sgiacomo.travaglini@arm.com 10212641Sgiacomo.travaglini@arm.com /** Address of the request. */ 10312641Sgiacomo.travaglini@arm.com Addr addr; 10412641Sgiacomo.travaglini@arm.com 10512641Sgiacomo.travaglini@arm.com /** Size of the request. */ 10612641Sgiacomo.travaglini@arm.com int size; 10712641Sgiacomo.travaglini@arm.com 10812641Sgiacomo.travaglini@arm.com /** True if the request has been sent to the bus. */ 10912641Sgiacomo.travaglini@arm.com bool inService; 11012641Sgiacomo.travaglini@arm.com 11112641Sgiacomo.travaglini@arm.com /** True if we will be putting the returned block in the cache */ 11212641Sgiacomo.travaglini@arm.com bool isCacheFill; 11312641Sgiacomo.travaglini@arm.com 11412641Sgiacomo.travaglini@arm.com /** True if we need to get an exclusive copy of the block. */ 11512641Sgiacomo.travaglini@arm.com bool needsExclusive() { return targets->needsExclusive; } 11612641Sgiacomo.travaglini@arm.com 11712641Sgiacomo.travaglini@arm.com /** True if the request is uncacheable */ 11812641Sgiacomo.travaglini@arm.com bool _isUncacheable; 11912641Sgiacomo.travaglini@arm.com 12012641Sgiacomo.travaglini@arm.com bool pendingInvalidate; 12112641Sgiacomo.travaglini@arm.com bool pendingShared; 12212641Sgiacomo.travaglini@arm.com 12312641Sgiacomo.travaglini@arm.com /** Thread number of the miss. */ 12412641Sgiacomo.travaglini@arm.com short threadNum; 12512641Sgiacomo.travaglini@arm.com /** The number of currently allocated targets. */ 12612641Sgiacomo.travaglini@arm.com short ntargets; 12712641Sgiacomo.travaglini@arm.com 12812641Sgiacomo.travaglini@arm.com 12912641Sgiacomo.travaglini@arm.com /** Data buffer (if needed). Currently used only for pending 13012641Sgiacomo.travaglini@arm.com * upgrade handling. */ 13112641Sgiacomo.travaglini@arm.com uint8_t *data; 13212641Sgiacomo.travaglini@arm.com 13312641Sgiacomo.travaglini@arm.com /** 13412641Sgiacomo.travaglini@arm.com * Pointer to this MSHR on the ready list. 13512641Sgiacomo.travaglini@arm.com * @sa MissQueue, MSHRQueue::readyList 13612641Sgiacomo.travaglini@arm.com */ 13712641Sgiacomo.travaglini@arm.com Iterator readyIter; 13812641Sgiacomo.travaglini@arm.com 13912641Sgiacomo.travaglini@arm.com /** 14012641Sgiacomo.travaglini@arm.com * Pointer to this MSHR on the allocated list. 14112641Sgiacomo.travaglini@arm.com * @sa MissQueue, MSHRQueue::allocatedList 14212641Sgiacomo.travaglini@arm.com */ 14312641Sgiacomo.travaglini@arm.com Iterator allocIter; 14412641Sgiacomo.travaglini@arm.com 14512641Sgiacomo.travaglini@arm.comprivate: 14612641Sgiacomo.travaglini@arm.com /** List of all requests that match the address */ 14712641Sgiacomo.travaglini@arm.com TargetList *targets; 14812641Sgiacomo.travaglini@arm.com 14912641Sgiacomo.travaglini@arm.com TargetList *deferredTargets; 15012641Sgiacomo.travaglini@arm.com 15112641Sgiacomo.travaglini@arm.compublic: 15212641Sgiacomo.travaglini@arm.com 15312641Sgiacomo.travaglini@arm.com bool isUncacheable() { return _isUncacheable; } 15412641Sgiacomo.travaglini@arm.com 15512641Sgiacomo.travaglini@arm.com /** 15612641Sgiacomo.travaglini@arm.com * Allocate a miss to this MSHR. 15712641Sgiacomo.travaglini@arm.com * @param cmd The requesting command. 15812641Sgiacomo.travaglini@arm.com * @param addr The address of the miss. 15912641Sgiacomo.travaglini@arm.com * @param asid The address space id of the miss. 16012641Sgiacomo.travaglini@arm.com * @param size The number of bytes to request. 16112641Sgiacomo.travaglini@arm.com * @param pkt The original miss. 16212641Sgiacomo.travaglini@arm.com */ 16312641Sgiacomo.travaglini@arm.com void allocate(Addr addr, int size, PacketPtr pkt, 16412641Sgiacomo.travaglini@arm.com Tick when, Counter _order); 16512641Sgiacomo.travaglini@arm.com 16612641Sgiacomo.travaglini@arm.com /** 16712641Sgiacomo.travaglini@arm.com * Mark this MSHR as free. 16812641Sgiacomo.travaglini@arm.com */ 16912641Sgiacomo.travaglini@arm.com void deallocate(); 17012641Sgiacomo.travaglini@arm.com 17112641Sgiacomo.travaglini@arm.com /** 17212641Sgiacomo.travaglini@arm.com * Add a request to the list of targets. 17312641Sgiacomo.travaglini@arm.com * @param target The target. 17412641Sgiacomo.travaglini@arm.com */ 17512641Sgiacomo.travaglini@arm.com void allocateTarget(PacketPtr target, Tick when, Counter order); 17612641Sgiacomo.travaglini@arm.com bool handleSnoop(PacketPtr target, Counter order); 17712641Sgiacomo.travaglini@arm.com 17812641Sgiacomo.travaglini@arm.com /** A simple constructor. */ 17912641Sgiacomo.travaglini@arm.com MSHR(); 18012641Sgiacomo.travaglini@arm.com /** A simple destructor. */ 18112641Sgiacomo.travaglini@arm.com ~MSHR(); 18212641Sgiacomo.travaglini@arm.com 18312641Sgiacomo.travaglini@arm.com /** 18412641Sgiacomo.travaglini@arm.com * Returns the current number of allocated targets. 18512641Sgiacomo.travaglini@arm.com * @return The current number of allocated targets. 18612641Sgiacomo.travaglini@arm.com */ 18712641Sgiacomo.travaglini@arm.com int getNumTargets() { return ntargets; } 18812641Sgiacomo.travaglini@arm.com 18912641Sgiacomo.travaglini@arm.com /** 19012641Sgiacomo.travaglini@arm.com * Returns a pointer to the target list. 19112641Sgiacomo.travaglini@arm.com * @return a pointer to the target list. 19212641Sgiacomo.travaglini@arm.com */ 19312641Sgiacomo.travaglini@arm.com TargetList *getTargetList() { return targets; } 19412641Sgiacomo.travaglini@arm.com 19512641Sgiacomo.travaglini@arm.com /** 19612641Sgiacomo.travaglini@arm.com * Returns true if there are targets left. 19712641Sgiacomo.travaglini@arm.com * @return true if there are targets 19812641Sgiacomo.travaglini@arm.com */ 19912641Sgiacomo.travaglini@arm.com bool hasTargets() { return !targets->empty(); } 20012641Sgiacomo.travaglini@arm.com 20112641Sgiacomo.travaglini@arm.com /** 20212641Sgiacomo.travaglini@arm.com * Returns a reference to the first target. 20312641Sgiacomo.travaglini@arm.com * @return A pointer to the first target. 20412641Sgiacomo.travaglini@arm.com */ 20512641Sgiacomo.travaglini@arm.com Target *getTarget() { assert(hasTargets()); return &targets->front(); } 20612641Sgiacomo.travaglini@arm.com 20712641Sgiacomo.travaglini@arm.com /** 20812641Sgiacomo.travaglini@arm.com * Pop first target. 20912641Sgiacomo.travaglini@arm.com */ 21012641Sgiacomo.travaglini@arm.com void popTarget() 21112641Sgiacomo.travaglini@arm.com { 21212641Sgiacomo.travaglini@arm.com --ntargets; 21312641Sgiacomo.travaglini@arm.com targets->pop_front(); 21412641Sgiacomo.travaglini@arm.com } 21512641Sgiacomo.travaglini@arm.com 21612641Sgiacomo.travaglini@arm.com bool isSimpleForward() 21712641Sgiacomo.travaglini@arm.com { 21812641Sgiacomo.travaglini@arm.com if (getNumTargets() != 1) 21912641Sgiacomo.travaglini@arm.com return false; 22012641Sgiacomo.travaglini@arm.com Target *tgt = getTarget(); 22112641Sgiacomo.travaglini@arm.com return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 22212641Sgiacomo.travaglini@arm.com } 22312641Sgiacomo.travaglini@arm.com 22412641Sgiacomo.travaglini@arm.com bool promoteDeferredTargets(); 22512641Sgiacomo.travaglini@arm.com 22612641Sgiacomo.travaglini@arm.com void handleFill(Packet *pkt, CacheBlk *blk); 22712641Sgiacomo.travaglini@arm.com 22812641Sgiacomo.travaglini@arm.com /** 22912641Sgiacomo.travaglini@arm.com * Prints the contents of this MSHR to stderr. 23012641Sgiacomo.travaglini@arm.com */ 23112641Sgiacomo.travaglini@arm.com void dump(); 23212641Sgiacomo.travaglini@arm.com}; 23312641Sgiacomo.travaglini@arm.com 23412641Sgiacomo.travaglini@arm.com#endif //__MSHR_HH__ 23512641Sgiacomo.travaglini@arm.com