mshr.hh revision 4871
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 */ 30 31/** 32 * @file 33 * Miss Status and Handling Register (MSHR) declaration. 34 */ 35 36#ifndef __MSHR_HH__ 37#define __MSHR_HH__ 38 39#include <list> 40 41#include "mem/packet.hh" 42 43class CacheBlk; 44class MSHRQueue; 45 46/** 47 * Miss Status and handling Register. This class keeps all the information 48 * needed to handle a cache miss including a list of target requests. 49 */ 50class MSHR : public Packet::SenderState 51{ 52 53 public: 54 55 class Target { 56 public: 57 Tick recvTime; //!< Time when request was received (for stats) 58 Tick readyTime; //!< Time when request is ready to be serviced 59 Counter order; //!< Global order (for memory consistency mgmt) 60 PacketPtr pkt; //!< Pending request packet. 61 bool cpuSide; //!< Did request come from cpu side or mem side? 62 63 bool isCpuSide() { return cpuSide; } 64 65 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide) 66 : recvTime(curTick), readyTime(_readyTime), order(_order), 67 pkt(_pkt), cpuSide(_cpuSide) 68 {} 69 }; 70 71 /** Defines the Data structure of the MSHR targetlist. */ 72 typedef std::list<Target> TargetList; 73 /** Target list iterator. */ 74 typedef std::list<Target>::iterator TargetListIterator; 75 /** A list of MSHRs. */ 76 typedef std::list<MSHR *> List; 77 /** MSHR list iterator. */ 78 typedef List::iterator Iterator; 79 /** MSHR list const_iterator. */ 80 typedef List::const_iterator ConstIterator; 81 82 /** Pointer to queue containing this MSHR. */ 83 MSHRQueue *queue; 84 85 /** Cycle when ready to issue */ 86 Tick readyTime; 87 88 /** Order number assigned by the miss queue. */ 89 Counter order; 90 91 /** Address of the request. */ 92 Addr addr; 93 94 /** Size of the request. */ 95 int size; 96 97 /** True if the request has been sent to the bus. */ 98 bool inService; 99 100 /** True if we will be putting the returned block in the cache */ 101 bool isCacheFill; 102 /** True if we need to get an exclusive copy of the block. */ 103 bool needsExclusive; 104 105 /** True if the request is uncacheable */ 106 bool _isUncacheable; 107 108 bool deferredNeedsExclusive; 109 bool pendingInvalidate; 110 bool pendingShared; 111 112 /** Thread number of the miss. */ 113 short threadNum; 114 /** The number of currently allocated targets. */ 115 short ntargets; 116 117 118 /** Data buffer (if needed). Currently used only for pending 119 * upgrade handling. */ 120 uint8_t *data; 121 122 /** 123 * Pointer to this MSHR on the ready list. 124 * @sa MissQueue, MSHRQueue::readyList 125 */ 126 Iterator readyIter; 127 128 /** 129 * Pointer to this MSHR on the allocated list. 130 * @sa MissQueue, MSHRQueue::allocatedList 131 */ 132 Iterator allocIter; 133 134private: 135 /** List of all requests that match the address */ 136 TargetList targets; 137 138 TargetList deferredTargets; 139 140public: 141 142 bool isUncacheable() { return _isUncacheable; } 143 144 /** 145 * Allocate a miss to this MSHR. 146 * @param cmd The requesting command. 147 * @param addr The address of the miss. 148 * @param asid The address space id of the miss. 149 * @param size The number of bytes to request. 150 * @param pkt The original miss. 151 */ 152 void allocate(Addr addr, int size, PacketPtr pkt, 153 Tick when, Counter _order); 154 155 /** 156 * Mark this MSHR as free. 157 */ 158 void deallocate(); 159 160 /** 161 * Add a request to the list of targets. 162 * @param target The target. 163 */ 164 void allocateTarget(PacketPtr target, Tick when, Counter order); 165 void allocateSnoopTarget(PacketPtr target, Tick when, Counter order); 166 167 /** A simple constructor. */ 168 MSHR(); 169 /** A simple destructor. */ 170 ~MSHR(); 171 172 /** 173 * Returns the current number of allocated targets. 174 * @return The current number of allocated targets. 175 */ 176 int getNumTargets() { return ntargets; } 177 178 /** 179 * Returns a pointer to the target list. 180 * @return a pointer to the target list. 181 */ 182 TargetList* getTargetList() { return &targets; } 183 184 /** 185 * Returns a reference to the first target. 186 * @return A pointer to the first target. 187 */ 188 Target *getTarget() { return &targets.front(); } 189 190 /** 191 * Pop first target. 192 */ 193 void popTarget() 194 { 195 --ntargets; 196 targets.pop_front(); 197 } 198 199 /** 200 * Returns true if there are targets left. 201 * @return true if there are targets 202 */ 203 bool hasTargets() { return !targets.empty(); } 204 205 bool isSimpleForward() 206 { 207 if (getNumTargets() != 1) 208 return false; 209 Target *tgt = getTarget(); 210 return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 211 } 212 213 bool promoteDeferredTargets(); 214 215 void handleFill(Packet *pkt, CacheBlk *blk); 216 217 /** 218 * Prints the contents of this MSHR to stderr. 219 */ 220 void dump(); 221}; 222 223#endif //__MSHR_HH__ 224