mshr.hh revision 12715
14309Sgblack@eecs.umich.edu/* 24309Sgblack@eecs.umich.edu * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 34309Sgblack@eecs.umich.edu * All rights reserved. 44309Sgblack@eecs.umich.edu * 54309Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 64309Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 74309Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 84309Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 94309Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 104309Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 114309Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 124309Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 134309Sgblack@eecs.umich.edu * 144309Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 154309Sgblack@eecs.umich.edu * All rights reserved. 164309Sgblack@eecs.umich.edu * 174309Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 184309Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 194309Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 204309Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 214309Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 224309Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 234309Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 244309Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 254309Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 264309Sgblack@eecs.umich.edu * this software without specific prior written permission. 274309Sgblack@eecs.umich.edu * 284309Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294309Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304309Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314309Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324309Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334309Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344309Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354309Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364309Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374309Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384309Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394309Sgblack@eecs.umich.edu * 404309Sgblack@eecs.umich.edu * Authors: Erik Hallnor 414309Sgblack@eecs.umich.edu */ 424309Sgblack@eecs.umich.edu 434309Sgblack@eecs.umich.edu/** 444309Sgblack@eecs.umich.edu * @file 454309Sgblack@eecs.umich.edu * Miss Status and Handling Register (MSHR) declaration. 464309Sgblack@eecs.umich.edu */ 474309Sgblack@eecs.umich.edu 484309Sgblack@eecs.umich.edu#ifndef __MEM_CACHE_MSHR_HH__ 494309Sgblack@eecs.umich.edu#define __MEM_CACHE_MSHR_HH__ 504309Sgblack@eecs.umich.edu 514309Sgblack@eecs.umich.edu#include <list> 524309Sgblack@eecs.umich.edu 534309Sgblack@eecs.umich.edu#include "base/printable.hh" 544309Sgblack@eecs.umich.edu#include "mem/cache/queue_entry.hh" 554309Sgblack@eecs.umich.edu 564309Sgblack@eecs.umich.educlass Cache; 574309Sgblack@eecs.umich.edu 584533Sgblack@eecs.umich.edu/** 594679Sgblack@eecs.umich.edu * Miss Status and handling Register. This class keeps all the information 604679Sgblack@eecs.umich.edu * needed to handle a cache miss including a list of target requests. 614679Sgblack@eecs.umich.edu * @sa \ref gem5MemorySystem "gem5 Memory System" 624533Sgblack@eecs.umich.edu */ 634533Sgblack@eecs.umich.educlass MSHR : public QueueEntry, public Printable 644537Sgblack@eecs.umich.edu{ 654533Sgblack@eecs.umich.edu 664528Sgblack@eecs.umich.edu /** 674528Sgblack@eecs.umich.edu * Consider the queues friends to avoid making everything public. 684528Sgblack@eecs.umich.edu */ 694528Sgblack@eecs.umich.edu template<typename Entry> 704528Sgblack@eecs.umich.edu friend class Queue; 714605Sgblack@eecs.umich.edu friend class MSHRQueue; 724528Sgblack@eecs.umich.edu 734528Sgblack@eecs.umich.edu private: 744528Sgblack@eecs.umich.edu 754615Sgblack@eecs.umich.edu /** Flag set by downstream caches */ 764615Sgblack@eecs.umich.edu bool downstreamPending; 774615Sgblack@eecs.umich.edu 785045Sgblack@eecs.umich.edu /** 795045Sgblack@eecs.umich.edu * Here we use one flag to track both if: 804615Sgblack@eecs.umich.edu * 814615Sgblack@eecs.umich.edu * 1. We are going to become owner or not, i.e., we will get the 824615Sgblack@eecs.umich.edu * block in an ownership state (Owned or Modified) with BlkDirty 834615Sgblack@eecs.umich.edu * set. This determines whether or not we are going to become the 844615Sgblack@eecs.umich.edu * responder and ordering point for future requests that we snoop. 854615Sgblack@eecs.umich.edu * 865029Sgblack@eecs.umich.edu * 2. We know that we are going to get a writable block, i.e. we 875029Sgblack@eecs.umich.edu * will get the block in writable state (Exclusive or Modified 884615Sgblack@eecs.umich.edu * state) with BlkWritable set. That determines whether additional 895029Sgblack@eecs.umich.edu * targets with needsWritable set will be able to be satisfied, or 905029Sgblack@eecs.umich.edu * if not should be put on the deferred list to possibly wait for 914615Sgblack@eecs.umich.edu * another request that does give us writable access. 924615Sgblack@eecs.umich.edu * 934863Sgblack@eecs.umich.edu * Condition 2 is actually just a shortcut that saves us from 944615Sgblack@eecs.umich.edu * possibly building a deferred target list and calling 954615Sgblack@eecs.umich.edu * promoteWritable() every time we get a writable block. Condition 964615Sgblack@eecs.umich.edu * 1, tracking ownership, is what is important. However, we never 974615Sgblack@eecs.umich.edu * receive ownership without marking the block dirty, and 984953Sgblack@eecs.umich.edu * consequently use pendingModified to track both ownership and 994615Sgblack@eecs.umich.edu * writability rather than having separate pendingDirty and 1004615Sgblack@eecs.umich.edu * pendingWritable flags. 1014863Sgblack@eecs.umich.edu */ 1024863Sgblack@eecs.umich.edu bool pendingModified; 1034863Sgblack@eecs.umich.edu 1044863Sgblack@eecs.umich.edu /** Did we snoop an invalidate while waiting for data? */ 1054863Sgblack@eecs.umich.edu bool postInvalidate; 1064863Sgblack@eecs.umich.edu 1074863Sgblack@eecs.umich.edu /** Did we snoop a read while waiting for data? */ 1084620Sgblack@eecs.umich.edu bool postDowngrade; 1094620Sgblack@eecs.umich.edu 1104620Sgblack@eecs.umich.edu public: 1114615Sgblack@eecs.umich.edu 1124686Sgblack@eecs.umich.edu /** True if the entry is just a simple forward from an upper level */ 1134686Sgblack@eecs.umich.edu bool isForward; 1144686Sgblack@eecs.umich.edu 1154686Sgblack@eecs.umich.edu class Target { 1164953Sgblack@eecs.umich.edu public: 1174686Sgblack@eecs.umich.edu 1184686Sgblack@eecs.umich.edu enum Source { 1194686Sgblack@eecs.umich.edu FromCPU, 1204686Sgblack@eecs.umich.edu FromSnoop, 1214953Sgblack@eecs.umich.edu FromPrefetcher 1224953Sgblack@eecs.umich.edu }; 1234686Sgblack@eecs.umich.edu 1244686Sgblack@eecs.umich.edu const Tick recvTime; //!< Time when request was received (for stats) 1254686Sgblack@eecs.umich.edu const Tick readyTime; //!< Time when request is ready to be serviced 1264686Sgblack@eecs.umich.edu const Counter order; //!< Global order (for memory consistency mgmt) 1274615Sgblack@eecs.umich.edu const PacketPtr pkt; //!< Pending request packet. 1284615Sgblack@eecs.umich.edu const Source source; //!< Request from cpu, memory, or prefetcher? 1294615Sgblack@eecs.umich.edu 1304615Sgblack@eecs.umich.edu /** 1314615Sgblack@eecs.umich.edu * We use this flag to track whether we have cleared the 1324615Sgblack@eecs.umich.edu * downstreamPending flag for the MSHR of the cache above 1334615Sgblack@eecs.umich.edu * where this packet originates from and guard noninitial 1345008Sgblack@eecs.umich.edu * attempts to clear it. 1355008Sgblack@eecs.umich.edu * 1365008Sgblack@eecs.umich.edu * The flag markedPending needs to be updated when the 1375008Sgblack@eecs.umich.edu * TargetList is in service which can be: 1385008Sgblack@eecs.umich.edu * 1) during the Target instantiation if the MSHR is in 1395082Sgblack@eecs.umich.edu * service and the target is not deferred, 1405082Sgblack@eecs.umich.edu * 2) when the MSHR becomes in service if the target is not 1415082Sgblack@eecs.umich.edu * deferred, 1425082Sgblack@eecs.umich.edu * 3) or when the TargetList is promoted (deferredTargets -> 1435082Sgblack@eecs.umich.edu * targets). 1444528Sgblack@eecs.umich.edu */ 1454528Sgblack@eecs.umich.edu bool markedPending; 146 147 const bool allocOnFill; //!< Should the response servicing this 148 //!< target list allocate in the cache? 149 150 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 151 Source _source, bool _markedPending, bool alloc_on_fill) 152 : recvTime(curTick()), readyTime(_readyTime), order(_order), 153 pkt(_pkt), source(_source), markedPending(_markedPending), 154 allocOnFill(alloc_on_fill) 155 {} 156 }; 157 158 class TargetList : public std::list<Target> { 159 160 public: 161 bool needsWritable; 162 bool hasUpgrade; 163 /** Set when the response should allocate on fill */ 164 bool allocOnFill; 165 /** 166 * Determine whether there was at least one non-snooping 167 * target coming from another cache. 168 */ 169 bool hasFromCache; 170 171 TargetList(); 172 173 /** 174 * Use the provided packet and the source to update the 175 * flags of this TargetList. 176 * 177 * @param pkt Packet considered for the flag update 178 * @param source Indicates the source of the packet 179 * @param alloc_on_fill Whether the pkt would allocate on a fill 180 */ 181 void updateFlags(PacketPtr pkt, Target::Source source, 182 bool alloc_on_fill); 183 184 void resetFlags() { 185 needsWritable = false; 186 hasUpgrade = false; 187 allocOnFill = false; 188 hasFromCache = false; 189 } 190 191 /** 192 * Goes through the list of targets and uses them to populate 193 * the flags of this TargetList. When the function returns the 194 * flags are consistent with the properties of packets in the 195 * list. 196 */ 197 void populateFlags(); 198 199 /** 200 * Tests if the flags of this TargetList have their default 201 * values. 202 */ 203 bool isReset() const { 204 return !needsWritable && !hasUpgrade && !allocOnFill && 205 !hasFromCache; 206 } 207 208 /** 209 * Add the specified packet in the TargetList. This function 210 * stores information related to the added packet and updates 211 * accordingly the flags. 212 * 213 * @param pkt Packet considered for adding 214 * @param readTime Tick at which the packet is processed by this cache 215 * @param order A counter giving a unique id to each target 216 * @param source Indicates the source agent of the packet 217 * @param markPending Set for deferred targets or pending MSHRs 218 * @param alloc_on_fill Whether it should allocate on a fill 219 */ 220 void add(PacketPtr pkt, Tick readyTime, Counter order, 221 Target::Source source, bool markPending, 222 bool alloc_on_fill); 223 224 /** 225 * Convert upgrades to the equivalent request if the cache line they 226 * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail). 227 * Used to rejig ordering between targets waiting on an MSHR. */ 228 void replaceUpgrades(); 229 230 void clearDownstreamPending(); 231 bool checkFunctional(PacketPtr pkt); 232 void print(std::ostream &os, int verbosity, 233 const std::string &prefix) const; 234 }; 235 236 /** A list of MSHRs. */ 237 typedef std::list<MSHR *> List; 238 /** MSHR list iterator. */ 239 typedef List::iterator Iterator; 240 241 /** The pending* and post* flags are only valid if inService is 242 * true. Using the accessor functions lets us detect if these 243 * flags are accessed improperly. 244 */ 245 246 /** True if we need to get a writable copy of the block. */ 247 bool needsWritable() const { return targets.needsWritable; } 248 249 bool isCleaning() const { 250 PacketPtr pkt = targets.front().pkt; 251 return pkt->isClean(); 252 } 253 254 bool isPendingModified() const { 255 assert(inService); return pendingModified; 256 } 257 258 bool hasPostInvalidate() const { 259 assert(inService); return postInvalidate; 260 } 261 262 bool hasPostDowngrade() const { 263 assert(inService); return postDowngrade; 264 } 265 266 bool sendPacket(Cache &cache); 267 268 bool allocOnFill() const { 269 return targets.allocOnFill; 270 } 271 272 /** 273 * Determine if there are non-deferred requests from other caches 274 * 275 * @return true if any of the targets is from another cache 276 */ 277 bool hasFromCache() const { 278 return targets.hasFromCache; 279 } 280 281 private: 282 283 /** 284 * Pointer to this MSHR on the ready list. 285 * @sa MissQueue, MSHRQueue::readyList 286 */ 287 Iterator readyIter; 288 289 /** 290 * Pointer to this MSHR on the allocated list. 291 * @sa MissQueue, MSHRQueue::allocatedList 292 */ 293 Iterator allocIter; 294 295 /** List of all requests that match the address */ 296 TargetList targets; 297 298 TargetList deferredTargets; 299 300 public: 301 302 /** 303 * Allocate a miss to this MSHR. 304 * @param blk_addr The address of the block. 305 * @param blk_size The number of bytes to request. 306 * @param pkt The original miss. 307 * @param when_ready When should the MSHR be ready to act upon. 308 * @param _order The logical order of this MSHR 309 * @param alloc_on_fill Should the cache allocate a block on fill 310 */ 311 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 312 Tick when_ready, Counter _order, bool alloc_on_fill); 313 314 void markInService(bool pending_modified_resp); 315 316 void clearDownstreamPending(); 317 318 /** 319 * Mark this MSHR as free. 320 */ 321 void deallocate(); 322 323 /** 324 * Add a request to the list of targets. 325 * @param target The target. 326 */ 327 void allocateTarget(PacketPtr target, Tick when, Counter order, 328 bool alloc_on_fill); 329 bool handleSnoop(PacketPtr target, Counter order); 330 331 /** A simple constructor. */ 332 MSHR(); 333 334 /** 335 * Returns the current number of allocated targets. 336 * @return The current number of allocated targets. 337 */ 338 int getNumTargets() const 339 { return targets.size() + deferredTargets.size(); } 340 341 /** 342 * Extracts the subset of the targets that can be serviced given a 343 * received response. This function returns the targets list 344 * unless the response is a ReadRespWithInvalidate. The 345 * ReadRespWithInvalidate is only invalidating response that its 346 * invalidation was not expected when the request (a 347 * ReadSharedReq) was sent out. For ReadRespWithInvalidate we can 348 * safely service only the first FromCPU target and all FromSnoop 349 * targets (inform all snoopers that we no longer have the block). 350 * 351 * @param pkt The response from the downstream memory 352 */ 353 TargetList extractServiceableTargets(PacketPtr pkt); 354 355 /** 356 * Returns true if there are targets left. 357 * @return true if there are targets 358 */ 359 bool hasTargets() const { return !targets.empty(); } 360 361 /** 362 * Returns a reference to the first target. 363 * @return A pointer to the first target. 364 */ 365 Target *getTarget() 366 { 367 assert(hasTargets()); 368 return &targets.front(); 369 } 370 371 /** 372 * Pop first target. 373 */ 374 void popTarget() 375 { 376 targets.pop_front(); 377 } 378 379 bool promoteDeferredTargets(); 380 381 void promoteWritable(); 382 383 bool checkFunctional(PacketPtr pkt); 384 385 /** 386 * Prints the contents of this MSHR for debugging. 387 */ 388 void print(std::ostream &os, 389 int verbosity = 0, 390 const std::string &prefix = "") const; 391 /** 392 * A no-args wrapper of print(std::ostream...) meant to be 393 * invoked from DPRINTFs avoiding string overheads in fast mode 394 * 395 * @return string with mshr fields + [deferred]targets 396 */ 397 std::string print() const; 398}; 399 400#endif // __MEM_CACHE_MSHR_HH__ 401