mshr.hh revision 11742
12810SN/A/*
211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
412810SN/A */
422810SN/A
432810SN/A/**
442810SN/A * @file
452810SN/A * Miss Status and Handling Register (MSHR) declaration.
462810SN/A */
472810SN/A
4810764Sandreas.hansson@arm.com#ifndef __MEM_CACHE_MSHR_HH__
4910764Sandreas.hansson@arm.com#define __MEM_CACHE_MSHR_HH__
502810SN/A
514626SN/A#include <list>
524626SN/A
535314SN/A#include "base/printable.hh"
5411375Sandreas.hansson@arm.com#include "mem/cache/queue_entry.hh"
552810SN/A
5611375Sandreas.hansson@arm.comclass Cache;
572810SN/A
582810SN/A/**
592810SN/A * Miss Status and handling Register. This class keeps all the information
603374SN/A * needed to handle a cache miss including a list of target requests.
619264Sdjordje.kovacevic@arm.com * @sa  \ref gem5MemorySystem "gem5 Memory System"
622810SN/A */
6311375Sandreas.hansson@arm.comclass MSHR : public QueueEntry, public Printable
644626SN/A{
654626SN/A
669725Sandreas.hansson@arm.com    /**
6711375Sandreas.hansson@arm.com     * Consider the queues friends to avoid making everything public.
689725Sandreas.hansson@arm.com     */
6911375Sandreas.hansson@arm.com    template<typename Entry>
7011375Sandreas.hansson@arm.com    friend class Queue;
719725Sandreas.hansson@arm.com    friend class MSHRQueue;
729725Sandreas.hansson@arm.com
739725Sandreas.hansson@arm.com  private:
749725Sandreas.hansson@arm.com
759725Sandreas.hansson@arm.com    /** Flag set by downstream caches */
769725Sandreas.hansson@arm.com    bool downstreamPending;
779725Sandreas.hansson@arm.com
7811284Sandreas.hansson@arm.com    /**
7911284Sandreas.hansson@arm.com     * Here we use one flag to track both if:
8011284Sandreas.hansson@arm.com     *
8111284Sandreas.hansson@arm.com     * 1. We are going to become owner or not, i.e., we will get the
8211284Sandreas.hansson@arm.com     * block in an ownership state (Owned or Modified) with BlkDirty
8311284Sandreas.hansson@arm.com     * set. This determines whether or not we are going to become the
8411284Sandreas.hansson@arm.com     * responder and ordering point for future requests that we snoop.
8511284Sandreas.hansson@arm.com     *
8611284Sandreas.hansson@arm.com     * 2. We know that we are going to get a writable block, i.e. we
8711284Sandreas.hansson@arm.com     * will get the block in writable state (Exclusive or Modified
8811284Sandreas.hansson@arm.com     * state) with BlkWritable set. That determines whether additional
8911284Sandreas.hansson@arm.com     * targets with needsWritable set will be able to be satisfied, or
9011284Sandreas.hansson@arm.com     * if not should be put on the deferred list to possibly wait for
9111284Sandreas.hansson@arm.com     * another request that does give us writable access.
9211284Sandreas.hansson@arm.com     *
9311284Sandreas.hansson@arm.com     * Condition 2 is actually just a shortcut that saves us from
9411284Sandreas.hansson@arm.com     * possibly building a deferred target list and calling
9511284Sandreas.hansson@arm.com     * promoteWritable() every time we get a writable block. Condition
9611284Sandreas.hansson@arm.com     * 1, tracking ownership, is what is important. However, we never
9711284Sandreas.hansson@arm.com     * receive ownership without marking the block dirty, and
9811284Sandreas.hansson@arm.com     * consequently use pendingModified to track both ownership and
9911284Sandreas.hansson@arm.com     * writability rather than having separate pendingDirty and
10011284Sandreas.hansson@arm.com     * pendingWritable flags.
10111284Sandreas.hansson@arm.com     */
10211284Sandreas.hansson@arm.com    bool pendingModified;
1039725Sandreas.hansson@arm.com
1049725Sandreas.hansson@arm.com    /** Did we snoop an invalidate while waiting for data? */
1059725Sandreas.hansson@arm.com    bool postInvalidate;
1069725Sandreas.hansson@arm.com
1079725Sandreas.hansson@arm.com    /** Did we snoop a read while waiting for data? */
1089725Sandreas.hansson@arm.com    bool postDowngrade;
1099725Sandreas.hansson@arm.com
1102810SN/A  public:
1114626SN/A
11211375Sandreas.hansson@arm.com    /** True if the entry is just a simple forward from an upper level */
11311375Sandreas.hansson@arm.com    bool isForward;
11411375Sandreas.hansson@arm.com
1154626SN/A    class Target {
1164626SN/A      public:
1175875Ssteve.reinhardt@amd.com
1185875Ssteve.reinhardt@amd.com        enum Source {
1195875Ssteve.reinhardt@amd.com            FromCPU,
1205875Ssteve.reinhardt@amd.com            FromSnoop,
1215875Ssteve.reinhardt@amd.com            FromPrefetcher
1225875Ssteve.reinhardt@amd.com        };
1235875Ssteve.reinhardt@amd.com
12410766Sandreas.hansson@arm.com        const Tick recvTime;  //!< Time when request was received (for stats)
12510766Sandreas.hansson@arm.com        const Tick readyTime; //!< Time when request is ready to be serviced
12610766Sandreas.hansson@arm.com        const Counter order;  //!< Global order (for memory consistency mgmt)
12710766Sandreas.hansson@arm.com        const PacketPtr pkt;  //!< Pending request packet.
12810766Sandreas.hansson@arm.com        const Source source;  //!< Request from cpu, memory, or prefetcher?
12911742Snikos.nikoleris@arm.com
13011742Snikos.nikoleris@arm.com        /**
13111742Snikos.nikoleris@arm.com         * We use this flag to track whether we have cleared the
13211742Snikos.nikoleris@arm.com         * downstreamPending flag for the MSHR of the cache above
13311742Snikos.nikoleris@arm.com         * where this packet originates from and guard noninitial
13411742Snikos.nikoleris@arm.com         * attempts to clear it.
13511742Snikos.nikoleris@arm.com         *
13611742Snikos.nikoleris@arm.com         * The flag markedPending needs to be updated when the
13711742Snikos.nikoleris@arm.com         * TargetList is in service which can be:
13811742Snikos.nikoleris@arm.com         * 1) during the Target instantiation if the MSHR is in
13911742Snikos.nikoleris@arm.com         * service and the target is not deferred,
14011742Snikos.nikoleris@arm.com         * 2) when the MSHR becomes in service if the target is not
14111742Snikos.nikoleris@arm.com         * deferred,
14211742Snikos.nikoleris@arm.com         * 3) or when the TargetList is promoted (deferredTargets ->
14311742Snikos.nikoleris@arm.com         * targets).
14411742Snikos.nikoleris@arm.com         */
14511742Snikos.nikoleris@arm.com        bool markedPending;
14611742Snikos.nikoleris@arm.com
14711741Snikos.nikoleris@arm.com        const bool allocOnFill;   //!< Should the response servicing this
14811741Snikos.nikoleris@arm.com                                  //!< target list allocate in the cache?
1494626SN/A
1505318SN/A        Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
15111741Snikos.nikoleris@arm.com               Source _source, bool _markedPending, bool alloc_on_fill)
1527823Ssteve.reinhardt@amd.com            : recvTime(curTick()), readyTime(_readyTime), order(_order),
15311741Snikos.nikoleris@arm.com              pkt(_pkt), source(_source), markedPending(_markedPending),
15411741Snikos.nikoleris@arm.com              allocOnFill(alloc_on_fill)
1554626SN/A        {}
1564626SN/A    };
1574626SN/A
1584903SN/A    class TargetList : public std::list<Target> {
1594903SN/A
1604903SN/A      public:
16111284Sandreas.hansson@arm.com        bool needsWritable;
1624903SN/A        bool hasUpgrade;
16311741Snikos.nikoleris@arm.com        /** Set when the response should allocate on fill */
16411741Snikos.nikoleris@arm.com        bool allocOnFill;
1654903SN/A
1664903SN/A        TargetList();
16711740Snikos.nikoleris@arm.com
16811740Snikos.nikoleris@arm.com        /**
16911740Snikos.nikoleris@arm.com         * Use the provided packet and the source to update the
17011740Snikos.nikoleris@arm.com         * flags of this TargetList.
17111740Snikos.nikoleris@arm.com         *
17211740Snikos.nikoleris@arm.com         * @param pkt Packet considered for the flag update
17311740Snikos.nikoleris@arm.com         * @param source Indicates the source of the packet
17411741Snikos.nikoleris@arm.com         * @param alloc_on_fill Whether the pkt would allocate on a fill
17511740Snikos.nikoleris@arm.com         */
17611741Snikos.nikoleris@arm.com        void updateFlags(PacketPtr pkt, Target::Source source,
17711741Snikos.nikoleris@arm.com                         bool alloc_on_fill);
17811740Snikos.nikoleris@arm.com
17911741Snikos.nikoleris@arm.com        void resetFlags() { needsWritable = hasUpgrade = allocOnFill = false; }
18011740Snikos.nikoleris@arm.com
18111740Snikos.nikoleris@arm.com        /**
18211740Snikos.nikoleris@arm.com         * Goes through the list of targets and uses them to populate
18311740Snikos.nikoleris@arm.com         * the flags of this TargetList. When the function returns the
18411740Snikos.nikoleris@arm.com         * flags are consistent with the properties of packets in the
18511740Snikos.nikoleris@arm.com         * list.
18611740Snikos.nikoleris@arm.com         */
18711740Snikos.nikoleris@arm.com        void populateFlags();
18811740Snikos.nikoleris@arm.com
18911741Snikos.nikoleris@arm.com        /**
19011741Snikos.nikoleris@arm.com         * Tests if the flags of this TargetList have their default
19111741Snikos.nikoleris@arm.com         * values.
19211741Snikos.nikoleris@arm.com         */
19311741Snikos.nikoleris@arm.com        bool isReset() const {
19411741Snikos.nikoleris@arm.com            return !needsWritable && !hasUpgrade && !allocOnFill;
19511741Snikos.nikoleris@arm.com        }
19611741Snikos.nikoleris@arm.com
19711741Snikos.nikoleris@arm.com        /**
19811741Snikos.nikoleris@arm.com         * Add the specified packet in the TargetList. This function
19911741Snikos.nikoleris@arm.com         * stores information related to the added packet and updates
20011741Snikos.nikoleris@arm.com         * accordingly the flags.
20111741Snikos.nikoleris@arm.com         *
20211741Snikos.nikoleris@arm.com         * @param pkt Packet considered for adding
20311741Snikos.nikoleris@arm.com         * @param readTime Tick at which the packet is processed by this cache
20411741Snikos.nikoleris@arm.com         * @param order A counter giving a unique id to each target
20511741Snikos.nikoleris@arm.com         * @param source Indicates the source agent of the packet
20611741Snikos.nikoleris@arm.com         * @param markPending Set for deferred targets or pending MSHRs
20711741Snikos.nikoleris@arm.com         * @param alloc_on_fill Whether it should allocate on a fill
20811741Snikos.nikoleris@arm.com         */
2095318SN/A        void add(PacketPtr pkt, Tick readyTime, Counter order,
21011741Snikos.nikoleris@arm.com                 Target::Source source, bool markPending,
21111741Snikos.nikoleris@arm.com                 bool alloc_on_fill);
21211357Sstephan.diestelhorst@arm.com
21311357Sstephan.diestelhorst@arm.com        /**
21411357Sstephan.diestelhorst@arm.com         * Convert upgrades to the equivalent request if the cache line they
21511357Sstephan.diestelhorst@arm.com         * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
21611357Sstephan.diestelhorst@arm.com         * Used to rejig ordering between targets waiting on an MSHR. */
2174903SN/A        void replaceUpgrades();
21811357Sstephan.diestelhorst@arm.com
2194908SN/A        void clearDownstreamPending();
2204920SN/A        bool checkFunctional(PacketPtr pkt);
2215314SN/A        void print(std::ostream &os, int verbosity,
2225314SN/A                   const std::string &prefix) const;
2234903SN/A    };
2244903SN/A
2252810SN/A    /** A list of MSHRs. */
2262810SN/A    typedef std::list<MSHR *> List;
2272810SN/A    /** MSHR list iterator. */
2282810SN/A    typedef List::iterator Iterator;
2294903SN/A
2307667Ssteve.reinhardt@amd.com    /** The pending* and post* flags are only valid if inService is
2317667Ssteve.reinhardt@amd.com     *  true.  Using the accessor functions lets us detect if these
2327667Ssteve.reinhardt@amd.com     *  flags are accessed improperly.
2337667Ssteve.reinhardt@amd.com     */
2347667Ssteve.reinhardt@amd.com
23511284Sandreas.hansson@arm.com    /** True if we need to get a writable copy of the block. */
23611284Sandreas.hansson@arm.com    bool needsWritable() const { return targets.needsWritable; }
2379725Sandreas.hansson@arm.com
23811284Sandreas.hansson@arm.com    bool isPendingModified() const {
23911284Sandreas.hansson@arm.com        assert(inService); return pendingModified;
2407667Ssteve.reinhardt@amd.com    }
2417667Ssteve.reinhardt@amd.com
2427667Ssteve.reinhardt@amd.com    bool hasPostInvalidate() const {
2437667Ssteve.reinhardt@amd.com        assert(inService); return postInvalidate;
2447667Ssteve.reinhardt@amd.com    }
2457667Ssteve.reinhardt@amd.com
2467667Ssteve.reinhardt@amd.com    bool hasPostDowngrade() const {
2477667Ssteve.reinhardt@amd.com        assert(inService); return postDowngrade;
2487667Ssteve.reinhardt@amd.com    }
2494665SN/A
25011375Sandreas.hansson@arm.com    bool sendPacket(Cache &cache);
25111375Sandreas.hansson@arm.com
25211741Snikos.nikoleris@arm.com    bool allocOnFill() const {
25311741Snikos.nikoleris@arm.com        return targets.allocOnFill;
25411741Snikos.nikoleris@arm.com    }
2559725Sandreas.hansson@arm.com  private:
2564668SN/A
2572810SN/A    /**
2582810SN/A     * Pointer to this MSHR on the ready list.
2592810SN/A     * @sa MissQueue, MSHRQueue::readyList
2602810SN/A     */
2612810SN/A    Iterator readyIter;
2624626SN/A
2632810SN/A    /**
2642810SN/A     * Pointer to this MSHR on the allocated list.
2652810SN/A     * @sa MissQueue, MSHRQueue::allocatedList
2662810SN/A     */
2672810SN/A    Iterator allocIter;
2682810SN/A
2693374SN/A    /** List of all requests that match the address */
2709725Sandreas.hansson@arm.com    TargetList targets;
2712810SN/A
2729725Sandreas.hansson@arm.com    TargetList deferredTargets;
2734665SN/A
2749725Sandreas.hansson@arm.com  public:
2754626SN/A
2762810SN/A    /**
2772810SN/A     * Allocate a miss to this MSHR.
27810764Sandreas.hansson@arm.com     * @param blk_addr The address of the block.
27910764Sandreas.hansson@arm.com     * @param blk_size The number of bytes to request.
28010764Sandreas.hansson@arm.com     * @param pkt The original miss.
28110764Sandreas.hansson@arm.com     * @param when_ready When should the MSHR be ready to act upon.
28210764Sandreas.hansson@arm.com     * @param _order The logical order of this MSHR
28311197Sandreas.hansson@arm.com     * @param alloc_on_fill Should the cache allocate a block on fill
2842810SN/A     */
28510764Sandreas.hansson@arm.com    void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
28611197Sandreas.hansson@arm.com                  Tick when_ready, Counter _order, bool alloc_on_fill);
2872810SN/A
28811375Sandreas.hansson@arm.com    void markInService(bool pending_modified_resp);
2894908SN/A
2905318SN/A    void clearDownstreamPending();
2915318SN/A
2922810SN/A    /**
2932810SN/A     * Mark this MSHR as free.
2942810SN/A     */
2952810SN/A    void deallocate();
2962810SN/A
2972810SN/A    /**
2983374SN/A     * Add a request to the list of targets.
2992810SN/A     * @param target The target.
3002810SN/A     */
30111197Sandreas.hansson@arm.com    void allocateTarget(PacketPtr target, Tick when, Counter order,
30211197Sandreas.hansson@arm.com                        bool alloc_on_fill);
3034902SN/A    bool handleSnoop(PacketPtr target, Counter order);
3042810SN/A
3052810SN/A    /** A simple constructor. */
3062810SN/A    MSHR();
3072810SN/A
3082810SN/A    /**
3092810SN/A     * Returns the current number of allocated targets.
3102810SN/A     * @return The current number of allocated targets.
3112810SN/A     */
3129725Sandreas.hansson@arm.com    int getNumTargets() const
3139725Sandreas.hansson@arm.com    { return targets.size() + deferredTargets.size(); }
3142810SN/A
3152810SN/A    /**
31611742Snikos.nikoleris@arm.com     * Extracts the subset of the targets that can be serviced given a
31711742Snikos.nikoleris@arm.com     * received response. This function returns the targets list
31811742Snikos.nikoleris@arm.com     * unless the response is a ReadRespWithInvalidate. The
31911742Snikos.nikoleris@arm.com     * ReadRespWithInvalidate is only invalidating response that its
32011742Snikos.nikoleris@arm.com     * invalidation was not expected when the request (a
32111742Snikos.nikoleris@arm.com     * ReadSharedReq) was sent out. For ReadRespWithInvalidate we can
32211742Snikos.nikoleris@arm.com     * safely service only the first FromCPU target and all FromSnoop
32311742Snikos.nikoleris@arm.com     * targets (inform all snoopers that we no longer have the block).
32411742Snikos.nikoleris@arm.com     *
32511742Snikos.nikoleris@arm.com     * @param pkt The response from the downstream memory
32611742Snikos.nikoleris@arm.com     */
32711742Snikos.nikoleris@arm.com    TargetList extractServiceableTargets(PacketPtr pkt);
32811742Snikos.nikoleris@arm.com
32911742Snikos.nikoleris@arm.com    /**
3304899SN/A     * Returns true if there are targets left.
3314899SN/A     * @return true if there are targets
3324899SN/A     */
3339725Sandreas.hansson@arm.com    bool hasTargets() const { return !targets.empty(); }
3344899SN/A
3354899SN/A    /**
3362810SN/A     * Returns a reference to the first target.
3372810SN/A     * @return A pointer to the first target.
3382810SN/A     */
3399725Sandreas.hansson@arm.com    Target *getTarget()
3405730SSteve.Reinhardt@amd.com    {
3415730SSteve.Reinhardt@amd.com        assert(hasTargets());
3429725Sandreas.hansson@arm.com        return &targets.front();
3435730SSteve.Reinhardt@amd.com    }
3442810SN/A
3452810SN/A    /**
3462810SN/A     * Pop first target.
3472810SN/A     */
3482810SN/A    void popTarget()
3492810SN/A    {
3509725Sandreas.hansson@arm.com        targets.pop_front();
3512810SN/A    }
3522810SN/A
3534665SN/A    bool promoteDeferredTargets();
3544665SN/A
35511284Sandreas.hansson@arm.com    void promoteWritable();
3564668SN/A
3575314SN/A    bool checkFunctional(PacketPtr pkt);
3584920SN/A
3592810SN/A    /**
3605314SN/A     * Prints the contents of this MSHR for debugging.
3612810SN/A     */
3625314SN/A    void print(std::ostream &os,
3635314SN/A               int verbosity = 0,
3645314SN/A               const std::string &prefix = "") const;
3659663Suri.wiener@arm.com    /**
3669663Suri.wiener@arm.com     * A no-args wrapper of print(std::ostream...)  meant to be
3679663Suri.wiener@arm.com     * invoked from DPRINTFs avoiding string overheads in fast mode
3689663Suri.wiener@arm.com     *
3699663Suri.wiener@arm.com     * @return string with mshr fields + [deferred]targets
3709663Suri.wiener@arm.com     */
3719663Suri.wiener@arm.com    std::string print() const;
3722810SN/A};
3732810SN/A
37410764Sandreas.hansson@arm.com#endif // __MEM_CACHE_MSHR_HH__
375