mshr.cc revision 9725:0d4ee33078bb
110259SAndrew.Bardsley@arm.com/*
210259SAndrew.Bardsley@arm.com * Copyright (c) 2012 ARM Limited
310259SAndrew.Bardsley@arm.com * All rights reserved.
410259SAndrew.Bardsley@arm.com *
510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall
610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual
710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating
810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software
910259SAndrew.Bardsley@arm.com * licensed hereunder.  You may use the software subject to the license
1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated
1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software,
1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form.
1310259SAndrew.Bardsley@arm.com *
1410259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
1510259SAndrew.Bardsley@arm.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
1610259SAndrew.Bardsley@arm.com * All rights reserved.
1710259SAndrew.Bardsley@arm.com *
1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without
1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are
2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright
2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer;
2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright
2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the
2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution;
2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its
2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from
2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission.
2810259SAndrew.Bardsley@arm.com *
2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4010259SAndrew.Bardsley@arm.com *
4110259SAndrew.Bardsley@arm.com * Authors: Erik Hallnor
4210259SAndrew.Bardsley@arm.com *          Dave Greene
4310259SAndrew.Bardsley@arm.com */
4410259SAndrew.Bardsley@arm.com
4510259SAndrew.Bardsley@arm.com/**
4610259SAndrew.Bardsley@arm.com * @file
4710259SAndrew.Bardsley@arm.com * Miss Status and Handling Register (MSHR) definitions.
4810259SAndrew.Bardsley@arm.com */
4910259SAndrew.Bardsley@arm.com
5010259SAndrew.Bardsley@arm.com#include <algorithm>
5110259SAndrew.Bardsley@arm.com#include <cassert>
5210259SAndrew.Bardsley@arm.com#include <string>
5310259SAndrew.Bardsley@arm.com#include <vector>
5410259SAndrew.Bardsley@arm.com
5510259SAndrew.Bardsley@arm.com#include "base/misc.hh"
5610259SAndrew.Bardsley@arm.com#include "base/types.hh"
5710259SAndrew.Bardsley@arm.com#include "debug/Cache.hh"
5810259SAndrew.Bardsley@arm.com#include "mem/cache/cache.hh"
5910259SAndrew.Bardsley@arm.com#include "mem/cache/mshr.hh"
6010259SAndrew.Bardsley@arm.com#include "sim/core.hh"
6110259SAndrew.Bardsley@arm.com
6210259SAndrew.Bardsley@arm.comusing namespace std;
6310259SAndrew.Bardsley@arm.com
6410259SAndrew.Bardsley@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
6510259SAndrew.Bardsley@arm.com               pendingDirty(false), postInvalidate(false),
6610259SAndrew.Bardsley@arm.com               postDowngrade(false), queue(NULL), order(0), addr(0), size(0),
6710259SAndrew.Bardsley@arm.com               inService(false), isForward(false), threadNum(InvalidThreadID),
6810259SAndrew.Bardsley@arm.com               data(NULL)
6910259SAndrew.Bardsley@arm.com{
7010259SAndrew.Bardsley@arm.com}
7110259SAndrew.Bardsley@arm.com
7210259SAndrew.Bardsley@arm.com
7310259SAndrew.Bardsley@arm.comMSHR::TargetList::TargetList()
7410259SAndrew.Bardsley@arm.com    : needsExclusive(false), hasUpgrade(false)
7510259SAndrew.Bardsley@arm.com{}
7610259SAndrew.Bardsley@arm.com
7710259SAndrew.Bardsley@arm.com
7810259SAndrew.Bardsley@arm.cominline void
7910259SAndrew.Bardsley@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
8010259SAndrew.Bardsley@arm.com                      Counter order, Target::Source source, bool markPending)
8110259SAndrew.Bardsley@arm.com{
8210259SAndrew.Bardsley@arm.com    if (source != Target::FromSnoop) {
8310259SAndrew.Bardsley@arm.com        if (pkt->needsExclusive()) {
8410259SAndrew.Bardsley@arm.com            needsExclusive = true;
8510259SAndrew.Bardsley@arm.com        }
8610259SAndrew.Bardsley@arm.com
8710259SAndrew.Bardsley@arm.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
8810259SAndrew.Bardsley@arm.com        // since it would have been failed already if we didn't have a
8910259SAndrew.Bardsley@arm.com        // read-only copy
9010259SAndrew.Bardsley@arm.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
9110259SAndrew.Bardsley@arm.com            hasUpgrade = true;
9210259SAndrew.Bardsley@arm.com        }
9310259SAndrew.Bardsley@arm.com    }
9410259SAndrew.Bardsley@arm.com
9510259SAndrew.Bardsley@arm.com    if (markPending) {
9610259SAndrew.Bardsley@arm.com        // Iterate over the SenderState stack and see if we find
9710259SAndrew.Bardsley@arm.com        // an MSHR entry. If we do, set the downstreamPending
9810259SAndrew.Bardsley@arm.com        // flag. Otherwise, do nothing.
9910259SAndrew.Bardsley@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
10010259SAndrew.Bardsley@arm.com        if (mshr != NULL) {
10110259SAndrew.Bardsley@arm.com            assert(!mshr->downstreamPending);
10210259SAndrew.Bardsley@arm.com            mshr->downstreamPending = true;
10310259SAndrew.Bardsley@arm.com        }
10410259SAndrew.Bardsley@arm.com    }
10510259SAndrew.Bardsley@arm.com
10610259SAndrew.Bardsley@arm.com    push_back(Target(pkt, readyTime, order, source, markPending));
10710259SAndrew.Bardsley@arm.com}
10810259SAndrew.Bardsley@arm.com
10910259SAndrew.Bardsley@arm.com
11010259SAndrew.Bardsley@arm.comstatic void
11110259SAndrew.Bardsley@arm.comreplaceUpgrade(PacketPtr pkt)
11210259SAndrew.Bardsley@arm.com{
11310259SAndrew.Bardsley@arm.com    if (pkt->cmd == MemCmd::UpgradeReq) {
11410259SAndrew.Bardsley@arm.com        pkt->cmd = MemCmd::ReadExReq;
11510259SAndrew.Bardsley@arm.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
11610259SAndrew.Bardsley@arm.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
11710259SAndrew.Bardsley@arm.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
11810259SAndrew.Bardsley@arm.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
11910259SAndrew.Bardsley@arm.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
12010259SAndrew.Bardsley@arm.com        pkt->cmd = MemCmd::StoreCondFailReq;
12110259SAndrew.Bardsley@arm.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
12210259SAndrew.Bardsley@arm.com    }
12310259SAndrew.Bardsley@arm.com}
12410259SAndrew.Bardsley@arm.com
12510259SAndrew.Bardsley@arm.com
12610259SAndrew.Bardsley@arm.comvoid
12710259SAndrew.Bardsley@arm.comMSHR::TargetList::replaceUpgrades()
12810259SAndrew.Bardsley@arm.com{
12910259SAndrew.Bardsley@arm.com    if (!hasUpgrade)
13010259SAndrew.Bardsley@arm.com        return;
13110259SAndrew.Bardsley@arm.com
13210259SAndrew.Bardsley@arm.com    Iterator end_i = end();
13310259SAndrew.Bardsley@arm.com    for (Iterator i = begin(); i != end_i; ++i) {
13410259SAndrew.Bardsley@arm.com        replaceUpgrade(i->pkt);
13510259SAndrew.Bardsley@arm.com    }
13610259SAndrew.Bardsley@arm.com
13710259SAndrew.Bardsley@arm.com    hasUpgrade = false;
13810259SAndrew.Bardsley@arm.com}
13910259SAndrew.Bardsley@arm.com
14010259SAndrew.Bardsley@arm.com
14110259SAndrew.Bardsley@arm.comvoid
14210259SAndrew.Bardsley@arm.comMSHR::TargetList::clearDownstreamPending()
14310259SAndrew.Bardsley@arm.com{
14410259SAndrew.Bardsley@arm.com    Iterator end_i = end();
14510259SAndrew.Bardsley@arm.com    for (Iterator i = begin(); i != end_i; ++i) {
14610259SAndrew.Bardsley@arm.com        if (i->markedPending) {
14710259SAndrew.Bardsley@arm.com            // Iterate over the SenderState stack and see if we find
14810259SAndrew.Bardsley@arm.com            // an MSHR entry. If we find one, clear the
14910259SAndrew.Bardsley@arm.com            // downstreamPending flag by calling
15010259SAndrew.Bardsley@arm.com            // clearDownstreamPending(). This recursively clears the
15110259SAndrew.Bardsley@arm.com            // downstreamPending flag in all caches this packet has
15210259SAndrew.Bardsley@arm.com            // passed through.
15310259SAndrew.Bardsley@arm.com            MSHR *mshr = i->pkt->findNextSenderState<MSHR>();
15410259SAndrew.Bardsley@arm.com            if (mshr != NULL) {
15510259SAndrew.Bardsley@arm.com                mshr->clearDownstreamPending();
15610259SAndrew.Bardsley@arm.com            }
15710259SAndrew.Bardsley@arm.com        }
15810259SAndrew.Bardsley@arm.com    }
15910259SAndrew.Bardsley@arm.com}
16010259SAndrew.Bardsley@arm.com
16110259SAndrew.Bardsley@arm.com
16210259SAndrew.Bardsley@arm.combool
16310259SAndrew.Bardsley@arm.comMSHR::TargetList::checkFunctional(PacketPtr pkt)
16410259SAndrew.Bardsley@arm.com{
16510259SAndrew.Bardsley@arm.com    Iterator end_i = end();
16610259SAndrew.Bardsley@arm.com    for (Iterator i = begin(); i != end_i; ++i) {
16710259SAndrew.Bardsley@arm.com        if (pkt->checkFunctional(i->pkt)) {
16810259SAndrew.Bardsley@arm.com            return true;
16910259SAndrew.Bardsley@arm.com        }
17010259SAndrew.Bardsley@arm.com    }
17110259SAndrew.Bardsley@arm.com
17210259SAndrew.Bardsley@arm.com    return false;
17310259SAndrew.Bardsley@arm.com}
17410259SAndrew.Bardsley@arm.com
17510259SAndrew.Bardsley@arm.com
17610259SAndrew.Bardsley@arm.comvoid
17710259SAndrew.Bardsley@arm.comMSHR::TargetList::
17810259SAndrew.Bardsley@arm.comprint(std::ostream &os, int verbosity, const std::string &prefix) const
17910259SAndrew.Bardsley@arm.com{
18010259SAndrew.Bardsley@arm.com    ConstIterator end_i = end();
18110259SAndrew.Bardsley@arm.com    for (ConstIterator i = begin(); i != end_i; ++i) {
18210259SAndrew.Bardsley@arm.com        const char *s;
18310259SAndrew.Bardsley@arm.com        switch (i->source) {
18410259SAndrew.Bardsley@arm.com          case Target::FromCPU:
18510259SAndrew.Bardsley@arm.com            s = "FromCPU";
18610259SAndrew.Bardsley@arm.com            break;
18710259SAndrew.Bardsley@arm.com          case Target::FromSnoop:
18810259SAndrew.Bardsley@arm.com            s = "FromSnoop";
18910259SAndrew.Bardsley@arm.com            break;
19010259SAndrew.Bardsley@arm.com          case Target::FromPrefetcher:
19110259SAndrew.Bardsley@arm.com            s = "FromPrefetcher";
19210259SAndrew.Bardsley@arm.com            break;
19310259SAndrew.Bardsley@arm.com          default:
19410259SAndrew.Bardsley@arm.com            s = "";
19510259SAndrew.Bardsley@arm.com            break;
19610259SAndrew.Bardsley@arm.com        }
19710259SAndrew.Bardsley@arm.com        ccprintf(os, "%s%s: ", prefix, s);
19810259SAndrew.Bardsley@arm.com        i->pkt->print(os, verbosity, "");
19910259SAndrew.Bardsley@arm.com    }
20010259SAndrew.Bardsley@arm.com}
20110259SAndrew.Bardsley@arm.com
20210259SAndrew.Bardsley@arm.com
20310259SAndrew.Bardsley@arm.comvoid
20410259SAndrew.Bardsley@arm.comMSHR::allocate(Addr _addr, int _size, PacketPtr target,
20510259SAndrew.Bardsley@arm.com               Tick whenReady, Counter _order)
20610259SAndrew.Bardsley@arm.com{
20710259SAndrew.Bardsley@arm.com    addr = _addr;
20810259SAndrew.Bardsley@arm.com    size = _size;
20910259SAndrew.Bardsley@arm.com    readyTime = whenReady;
21010259SAndrew.Bardsley@arm.com    order = _order;
21110259SAndrew.Bardsley@arm.com    assert(target);
21210259SAndrew.Bardsley@arm.com    isForward = false;
21310259SAndrew.Bardsley@arm.com    _isUncacheable = target->req->isUncacheable();
21410259SAndrew.Bardsley@arm.com    inService = false;
21510259SAndrew.Bardsley@arm.com    downstreamPending = false;
21610259SAndrew.Bardsley@arm.com    threadNum = 0;
21710259SAndrew.Bardsley@arm.com    assert(targets.isReset());
21810259SAndrew.Bardsley@arm.com    // Don't know of a case where we would allocate a new MSHR for a
21910259SAndrew.Bardsley@arm.com    // snoop (mem-side request), so set source according to request here
22010259SAndrew.Bardsley@arm.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
22110259SAndrew.Bardsley@arm.com        Target::FromPrefetcher : Target::FromCPU;
22210259SAndrew.Bardsley@arm.com    targets.add(target, whenReady, _order, source, true);
22310259SAndrew.Bardsley@arm.com    assert(deferredTargets.isReset());
22410259SAndrew.Bardsley@arm.com    data = NULL;
22510259SAndrew.Bardsley@arm.com}
22610259SAndrew.Bardsley@arm.com
22710259SAndrew.Bardsley@arm.com
22810259SAndrew.Bardsley@arm.comvoid
22910259SAndrew.Bardsley@arm.comMSHR::clearDownstreamPending()
23010259SAndrew.Bardsley@arm.com{
23110259SAndrew.Bardsley@arm.com    assert(downstreamPending);
23210259SAndrew.Bardsley@arm.com    downstreamPending = false;
23310259SAndrew.Bardsley@arm.com    // recursively clear flag on any MSHRs we will be forwarding
23410259SAndrew.Bardsley@arm.com    // responses to
23510259SAndrew.Bardsley@arm.com    targets.clearDownstreamPending();
23610259SAndrew.Bardsley@arm.com}
23710259SAndrew.Bardsley@arm.com
23810259SAndrew.Bardsley@arm.combool
23910259SAndrew.Bardsley@arm.comMSHR::markInService(PacketPtr pkt)
24010259SAndrew.Bardsley@arm.com{
24110259SAndrew.Bardsley@arm.com    assert(!inService);
24210259SAndrew.Bardsley@arm.com    if (isForwardNoResponse()) {
24310259SAndrew.Bardsley@arm.com        // we just forwarded the request packet & don't expect a
24410259SAndrew.Bardsley@arm.com        // response, so get rid of it
24510259SAndrew.Bardsley@arm.com        assert(getNumTargets() == 1);
24610259SAndrew.Bardsley@arm.com        popTarget();
24710259SAndrew.Bardsley@arm.com        return true;
24810259SAndrew.Bardsley@arm.com    }
24910259SAndrew.Bardsley@arm.com    inService = true;
25010259SAndrew.Bardsley@arm.com    pendingDirty = (targets.needsExclusive ||
25110259SAndrew.Bardsley@arm.com                    (!pkt->sharedAsserted() && pkt->memInhibitAsserted()));
25210259SAndrew.Bardsley@arm.com    postInvalidate = postDowngrade = false;
25310259SAndrew.Bardsley@arm.com
25410259SAndrew.Bardsley@arm.com    if (!downstreamPending) {
25510259SAndrew.Bardsley@arm.com        // let upstream caches know that the request has made it to a
25610259SAndrew.Bardsley@arm.com        // level where it's going to get a response
25710259SAndrew.Bardsley@arm.com        targets.clearDownstreamPending();
25810259SAndrew.Bardsley@arm.com    }
25910259SAndrew.Bardsley@arm.com    return false;
26010259SAndrew.Bardsley@arm.com}
26110259SAndrew.Bardsley@arm.com
26210259SAndrew.Bardsley@arm.com
26310259SAndrew.Bardsley@arm.comvoid
26410259SAndrew.Bardsley@arm.comMSHR::deallocate()
26510259SAndrew.Bardsley@arm.com{
26610259SAndrew.Bardsley@arm.com    assert(targets.empty());
26710259SAndrew.Bardsley@arm.com    targets.resetFlags();
26810259SAndrew.Bardsley@arm.com    assert(deferredTargets.isReset());
26910259SAndrew.Bardsley@arm.com    inService = false;
27010259SAndrew.Bardsley@arm.com}
27110259SAndrew.Bardsley@arm.com
27210259SAndrew.Bardsley@arm.com/*
27310259SAndrew.Bardsley@arm.com * Adds a target to an MSHR
27410259SAndrew.Bardsley@arm.com */
27510259SAndrew.Bardsley@arm.comvoid
27610259SAndrew.Bardsley@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
27710259SAndrew.Bardsley@arm.com{
27810259SAndrew.Bardsley@arm.com    // if there's a request already in service for this MSHR, we will
27910259SAndrew.Bardsley@arm.com    // have to defer the new target until after the response if any of
28010259SAndrew.Bardsley@arm.com    // the following are true:
28110259SAndrew.Bardsley@arm.com    // - there are other targets already deferred
28210259SAndrew.Bardsley@arm.com    // - there's a pending invalidate to be applied after the response
28310259SAndrew.Bardsley@arm.com    //   comes back (but before this target is processed)
28410259SAndrew.Bardsley@arm.com    // - this target requires an exclusive block and either we're not
28510259SAndrew.Bardsley@arm.com    //   getting an exclusive block back or we have already snooped
28610259SAndrew.Bardsley@arm.com    //   another read request that will downgrade our exclusive block
28710259SAndrew.Bardsley@arm.com    //   to shared
28810259SAndrew.Bardsley@arm.com
28910259SAndrew.Bardsley@arm.com    // assume we'd never issue a prefetch when we've got an
29010259SAndrew.Bardsley@arm.com    // outstanding miss
29110259SAndrew.Bardsley@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
29210259SAndrew.Bardsley@arm.com
29310259SAndrew.Bardsley@arm.com    if (inService &&
29410259SAndrew.Bardsley@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
295         (pkt->needsExclusive() &&
296          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
297        // need to put on deferred list
298        if (hasPostInvalidate())
299            replaceUpgrade(pkt);
300        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
301    } else {
302        // No request outstanding, or still OK to append to
303        // outstanding request: append to regular target list.  Only
304        // mark pending if current request hasn't been issued yet
305        // (isn't in service).
306        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
307    }
308}
309
310bool
311MSHR::handleSnoop(PacketPtr pkt, Counter _order)
312{
313    DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
314            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
315    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
316        // Request has not been issued yet, or it's been issued
317        // locally but is buffered unissued at some downstream cache
318        // which is forwarding us this snoop.  Either way, the packet
319        // we're snooping logically precedes this MSHR's request, so
320        // the snoop has no impact on the MSHR, but must be processed
321        // in the standard way by the cache.  The only exception is
322        // that if we're an L2+ cache buffering an UpgradeReq from a
323        // higher-level cache, and the snoop is invalidating, then our
324        // buffered upgrades must be converted to read exclusives,
325        // since the upper-level cache no longer has a valid copy.
326        // That is, even though the upper-level cache got out on its
327        // local bus first, some other invalidating transaction
328        // reached the global bus before the upgrade did.
329        if (pkt->needsExclusive()) {
330            targets.replaceUpgrades();
331            deferredTargets.replaceUpgrades();
332        }
333
334        return false;
335    }
336
337    // From here on down, the request issued by this MSHR logically
338    // precedes the request we're snooping.
339    if (pkt->needsExclusive()) {
340        // snooped request still precedes the re-request we'll have to
341        // issue for deferred targets, if any...
342        deferredTargets.replaceUpgrades();
343    }
344
345    if (hasPostInvalidate()) {
346        // a prior snoop has already appended an invalidation, so
347        // logically we don't have the block anymore; no need for
348        // further snooping.
349        return true;
350    }
351
352    if (isPendingDirty() || pkt->isInvalidate()) {
353        // We need to save and replay the packet in two cases:
354        // 1. We're awaiting an exclusive copy, so ownership is pending,
355        //    and we need to respond after we receive data.
356        // 2. It's an invalidation (e.g., UpgradeReq), and we need
357        //    to forward the snoop up the hierarchy after the current
358        //    transaction completes.
359
360        // Actual target device (typ. a memory) will delete the
361        // packet on reception, so we need to save a copy here.
362        PacketPtr cp_pkt = new Packet(pkt, true);
363        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
364                     downstreamPending && targets.needsExclusive);
365
366        if (isPendingDirty()) {
367            pkt->assertMemInhibit();
368            pkt->setSupplyExclusive();
369        }
370
371        if (pkt->needsExclusive()) {
372            // This transaction will take away our pending copy
373            postInvalidate = true;
374        }
375    }
376
377    if (!pkt->needsExclusive()) {
378        // This transaction will get a read-shared copy, downgrading
379        // our copy if we had an exclusive one
380        postDowngrade = true;
381        pkt->assertShared();
382    }
383
384    return true;
385}
386
387
388bool
389MSHR::promoteDeferredTargets()
390{
391    assert(targets.empty());
392    if (deferredTargets.empty()) {
393        return false;
394    }
395
396    // swap targets & deferredTargets lists
397    std::swap(targets, deferredTargets);
398
399    // clear deferredTargets flags
400    deferredTargets.resetFlags();
401
402    order = targets.front().order;
403    readyTime = std::max(curTick(), targets.front().readyTime);
404
405    return true;
406}
407
408
409void
410MSHR::handleFill(Packet *pkt, CacheBlk *blk)
411{
412    if (!pkt->sharedAsserted()
413        && !(hasPostInvalidate() || hasPostDowngrade())
414        && deferredTargets.needsExclusive) {
415        // We got an exclusive response, but we have deferred targets
416        // which are waiting to request an exclusive copy (not because
417        // of a pending invalidate).  This can happen if the original
418        // request was for a read-only (non-exclusive) block, but we
419        // got an exclusive copy anyway because of the E part of the
420        // MOESI/MESI protocol.  Since we got the exclusive copy
421        // there's no need to defer the targets, so move them up to
422        // the regular target list.
423        assert(!targets.needsExclusive);
424        targets.needsExclusive = true;
425        // if any of the deferred targets were upper-level cache
426        // requests marked downstreamPending, need to clear that
427        assert(!downstreamPending);  // not pending here anymore
428        deferredTargets.clearDownstreamPending();
429        // this clears out deferredTargets too
430        targets.splice(targets.end(), deferredTargets);
431        deferredTargets.resetFlags();
432    }
433}
434
435
436bool
437MSHR::checkFunctional(PacketPtr pkt)
438{
439    // For printing, we treat the MSHR as a whole as single entity.
440    // For other requests, we iterate over the individual targets
441    // since that's where the actual data lies.
442    if (pkt->isPrint()) {
443        pkt->checkFunctional(this, addr, size, NULL);
444        return false;
445    } else {
446        return (targets.checkFunctional(pkt) ||
447                deferredTargets.checkFunctional(pkt));
448    }
449}
450
451
452void
453MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
454{
455    ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s %s\n",
456             prefix, addr, addr+size-1,
457             isForward ? "Forward" : "",
458             isForwardNoResponse() ? "ForwNoResp" : "",
459             needsExclusive() ? "Excl" : "",
460             _isUncacheable ? "Unc" : "",
461             inService ? "InSvc" : "",
462             downstreamPending ? "DwnPend" : "",
463             hasPostInvalidate() ? "PostInv" : "",
464             hasPostDowngrade() ? "PostDowngr" : "");
465
466    ccprintf(os, "%s  Targets:\n", prefix);
467    targets.print(os, verbosity, prefix + "    ");
468    if (!deferredTargets.empty()) {
469        ccprintf(os, "%s  Deferred Targets:\n", prefix);
470        deferredTargets.print(os, verbosity, prefix + "      ");
471    }
472}
473
474std::string
475MSHR::print() const
476{
477    ostringstream str;
478    print(str);
479    return str.str();
480}
481