mshr.cc revision 12792:9af3470e24e7
12SN/A/*
21762SN/A * Copyright (c) 2012-2013, 2015-2018 ARM Limited
32SN/A * All rights reserved.
42SN/A *
52SN/A * The license below extends only to copyright in the software and shall
62SN/A * not be construed as granting a license to any other intellectual
72SN/A * property including but not limited to intellectual property relating
82SN/A * to a hardware implementation of the functionality of the software
92SN/A * licensed hereunder.  You may use the software subject to the license
102SN/A * terms below provided that you ensure that this notice is replicated
112SN/A * unmodified and in its entirety in all distributions of the software,
122SN/A * modified or unmodified, in source code or in binary form.
132SN/A *
142SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
152SN/A * Copyright (c) 2010 Advanced Micro Devices, Inc.
162SN/A * All rights reserved.
172SN/A *
182SN/A * Redistribution and use in source and binary forms, with or without
192SN/A * modification, are permitted provided that the following conditions are
202SN/A * met: redistributions of source code must retain the above copyright
212SN/A * notice, this list of conditions and the following disclaimer;
222SN/A * redistributions in binary form must reproduce the above copyright
232SN/A * notice, this list of conditions and the following disclaimer in the
242SN/A * documentation and/or other materials provided with the distribution;
252SN/A * neither the name of the copyright holders nor the names of its
262SN/A * contributors may be used to endorse or promote products derived from
272665Ssaidi@eecs.umich.edu * this software without specific prior written permission.
282665Ssaidi@eecs.umich.edu *
292665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
3775SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392439SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402439SN/A *
41603SN/A * Authors: Erik Hallnor
42603SN/A *          Dave Greene
432520SN/A */
442378SN/A
452378SN/A/**
46722SN/A * @file
472521SN/A * Miss Status and Handling Register (MSHR) definitions.
482378SN/A */
49312SN/A
501634SN/A#include "mem/cache/mshr.hh"
512680Sktlim@umich.edu
521634SN/A#include <cassert>
532521SN/A#include <string>
542378SN/A
552378SN/A#include "base/logging.hh"
56803SN/A#include "base/trace.hh"
572378SN/A#include "base/types.hh"
582SN/A#include "debug/Cache.hh"
592378SN/A#include "mem/cache/base.hh"
602SN/A#include "mem/request.hh"
612SN/A#include "sim/core.hh"
622SN/A
63603SN/AMSHR::MSHR() : downstreamPending(false),
642901Ssaidi@eecs.umich.edu               pendingModified(false),
652901Ssaidi@eecs.umich.edu               postInvalidate(false), postDowngrade(false),
662901Ssaidi@eecs.umich.edu               isForward(false)
672901Ssaidi@eecs.umich.edu{
682901Ssaidi@eecs.umich.edu}
692901Ssaidi@eecs.umich.edu
702901Ssaidi@eecs.umich.eduMSHR::TargetList::TargetList()
712901Ssaidi@eecs.umich.edu    : needsWritable(false), hasUpgrade(false), allocOnFill(false),
722901Ssaidi@eecs.umich.edu      hasFromCache(false)
732901Ssaidi@eecs.umich.edu{}
742901Ssaidi@eecs.umich.edu
752901Ssaidi@eecs.umich.edu
762901Ssaidi@eecs.umich.eduvoid
772901Ssaidi@eecs.umich.eduMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source,
782901Ssaidi@eecs.umich.edu                              bool alloc_on_fill)
792521SN/A{
802SN/A    if (source != Target::FromSnoop) {
812SN/A        if (pkt->needsWritable()) {
822680Sktlim@umich.edu            needsWritable = true;
831806SN/A        }
841806SN/A
851806SN/A        // StoreCondReq is effectively an upgrade if it's in an MSHR
861806SN/A        // since it would have been failed already if we didn't have a
872680Sktlim@umich.edu        // read-only copy
881806SN/A        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
891806SN/A            hasUpgrade = true;
901806SN/A        }
911806SN/A
92180SN/A        // potentially re-evaluate whether we should allocate on a fill or
932378SN/A        // not
942378SN/A        allocOnFill = allocOnFill || alloc_on_fill;
952378SN/A
962378SN/A        if (source != Target::FromPrefetcher) {
972520SN/A            hasFromCache = hasFromCache || pkt->fromCache();
982520SN/A        }
992520SN/A    }
1002521SN/A}
1012520SN/A
1021885SN/Avoid
1031070SN/AMSHR::TargetList::populateFlags()
104954SN/A{
1051070SN/A    resetFlags();
1061070SN/A    for (auto& t: *this) {
1071070SN/A        updateFlags(t.pkt, t.source, t.allocOnFill);
1081070SN/A    }
1091070SN/A}
1101070SN/A
1111070SN/Ainline void
1121070SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
1131070SN/A                      Counter order, Target::Source source, bool markPending,
1141070SN/A                      bool alloc_on_fill)
1151070SN/A{
1161070SN/A    updateFlags(pkt, source, alloc_on_fill);
1172378SN/A    if (markPending) {
1182378SN/A        // Iterate over the SenderState stack and see if we find
1192378SN/A        // an MSHR entry. If we do, set the downstreamPending
1202378SN/A        // flag. Otherwise, do nothing.
1212378SN/A        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1222378SN/A        if (mshr != nullptr) {
1232378SN/A            assert(!mshr->downstreamPending);
1241885SN/A            mshr->downstreamPending = true;
1251885SN/A        } else {
1262901Ssaidi@eecs.umich.edu            // No need to clear downstreamPending later
1272901Ssaidi@eecs.umich.edu            markPending = false;
1282424SN/A        }
1291885SN/A    }
1301885SN/A
1311885SN/A    emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill);
1321885SN/A}
1331885SN/A
1342158SN/A
1351885SN/Astatic void
1361885SN/AreplaceUpgrade(PacketPtr pkt)
1371885SN/A{
1381885SN/A    // remember if the current packet has data allocated
1391885SN/A    bool has_data = pkt->hasData() || pkt->hasRespData();
1401885SN/A
1411885SN/A    if (pkt->cmd == MemCmd::UpgradeReq) {
1421885SN/A        pkt->cmd = MemCmd::ReadExReq;
1431913SN/A        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1441885SN/A    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1451885SN/A        pkt->cmd = MemCmd::SCUpgradeFailReq;
1461885SN/A        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1471885SN/A    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1481885SN/A        pkt->cmd = MemCmd::StoreCondFailReq;
1491885SN/A        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1501885SN/A    }
1511885SN/A
1521885SN/A    if (!has_data) {
1531885SN/A        // there is no sensible way of setting the data field if the
1541885SN/A        // new command actually would carry data
1551885SN/A        assert(!pkt->hasData());
1561885SN/A
1571885SN/A        if (pkt->hasRespData()) {
1581885SN/A            // we went from a packet that had no data (neither request,
1591885SN/A            // nor response), to one that does, and therefore we need to
1602378SN/A            // actually allocate space for the data payload
16177SN/A            pkt->allocate();
1622378SN/A        }
1631070SN/A    }
1641070SN/A}
1652158SN/A
1662378SN/A
1671070SN/Avoid
1681070SN/AMSHR::TargetList::replaceUpgrades()
1691070SN/A{
1701070SN/A    if (!hasUpgrade)
1711070SN/A        return;
1722521SN/A
1732378SN/A    for (auto& t : *this) {
1742378SN/A        replaceUpgrade(t.pkt);
1751634SN/A    }
1762567SN/A
1771070SN/A    hasUpgrade = false;
1781070SN/A}
1791070SN/A
1802158SN/A
1812378SN/Avoid
1822158SN/AMSHR::TargetList::clearDownstreamPending(MSHR::TargetList::iterator begin,
1831070SN/A                                         MSHR::TargetList::iterator end)
1842158SN/A{
1852158SN/A    for (auto t = begin; t != end; t++) {
1861070SN/A        if (t->markedPending) {
1872158SN/A            // Iterate over the SenderState stack and see if we find
1881070SN/A            // an MSHR entry. If we find one, clear the
1892SN/A            // downstreamPending flag by calling
1902SN/A            // clearDownstreamPending(). This recursively clears the
1911129SN/A            // downstreamPending flag in all caches this packet has
1921129SN/A            // passed through.
1932158SN/A            MSHR *mshr = t->pkt->findNextSenderState<MSHR>();
1942158SN/A            if (mshr != nullptr) {
1951070SN/A                mshr->clearDownstreamPending();
1962378SN/A            }
1972378SN/A            t->markedPending = false;
1981070SN/A        }
1991070SN/A    }
2001070SN/A}
2011070SN/A
2021070SN/Avoid
2031070SN/AMSHR::TargetList::clearDownstreamPending()
2041070SN/A{
2051070SN/A    clearDownstreamPending(begin(), end());
2061070SN/A}
2071070SN/A
2081070SN/A
2091070SN/Abool
2101070SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
2111070SN/A{
2121070SN/A    for (auto& t : *this) {
2131070SN/A        if (pkt->checkFunctional(t.pkt)) {
2141070SN/A            return true;
2151070SN/A        }
2162378SN/A    }
2172378SN/A
2182378SN/A    return false;
2192378SN/A}
2202378SN/A
2212378SN/A
2222680Sktlim@umich.eduvoid
2232680Sktlim@umich.eduMSHR::TargetList::print(std::ostream &os, int verbosity,
2241070SN/A                        const std::string &prefix) const
2251070SN/A{
2261070SN/A    for (auto& t : *this) {
2272SN/A        const char *s;
22877SN/A        switch (t.source) {
2292SN/A          case Target::FromCPU:
2302SN/A            s = "FromCPU";
2312SN/A            break;
2322SN/A          case Target::FromSnoop:
2332SN/A            s = "FromSnoop";
2342SN/A            break;
2352SN/A          case Target::FromPrefetcher:
2362SN/A            s = "FromPrefetcher";
2372SN/A            break;
2382SN/A          default:
2392158SN/A            s = "";
2402158SN/A            break;
2412SN/A        }
2422SN/A        ccprintf(os, "%s%s: ", prefix, s);
2432SN/A        t.pkt->print(os, verbosity, "");
244        ccprintf(os, "\n");
245    }
246}
247
248
249void
250MSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
251               Tick when_ready, Counter _order, bool alloc_on_fill)
252{
253    blkAddr = blk_addr;
254    blkSize = blk_size;
255    isSecure = target->isSecure();
256    readyTime = when_ready;
257    order = _order;
258    assert(target);
259    isForward = false;
260    _isUncacheable = target->req->isUncacheable();
261    inService = false;
262    downstreamPending = false;
263    assert(targets.isReset());
264    // Don't know of a case where we would allocate a new MSHR for a
265    // snoop (mem-side request), so set source according to request here
266    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
267        Target::FromPrefetcher : Target::FromCPU;
268    targets.add(target, when_ready, _order, source, true, alloc_on_fill);
269    assert(deferredTargets.isReset());
270}
271
272
273void
274MSHR::clearDownstreamPending()
275{
276    assert(downstreamPending);
277    downstreamPending = false;
278    // recursively clear flag on any MSHRs we will be forwarding
279    // responses to
280    targets.clearDownstreamPending();
281}
282
283void
284MSHR::markInService(bool pending_modified_resp)
285{
286    assert(!inService);
287
288    inService = true;
289    pendingModified = targets.needsWritable || pending_modified_resp;
290    postInvalidate = postDowngrade = false;
291
292    if (!downstreamPending) {
293        // let upstream caches know that the request has made it to a
294        // level where it's going to get a response
295        targets.clearDownstreamPending();
296    }
297}
298
299
300void
301MSHR::deallocate()
302{
303    assert(targets.empty());
304    targets.resetFlags();
305    assert(deferredTargets.isReset());
306    inService = false;
307}
308
309/*
310 * Adds a target to an MSHR
311 */
312void
313MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
314                     bool alloc_on_fill)
315{
316    // assume we'd never issue a prefetch when we've got an
317    // outstanding miss
318    assert(pkt->cmd != MemCmd::HardPFReq);
319
320    // if there's a request already in service for this MSHR, we will
321    // have to defer the new target until after the response if any of
322    // the following are true:
323    // - there are other targets already deferred
324    // - there's a pending invalidate to be applied after the response
325    //   comes back (but before this target is processed)
326    // - the MSHR's first (and only) non-deferred target is a cache
327    //   maintenance packet
328    // - the new target is a cache maintenance packet (this is probably
329    //   overly conservative but certainly safe)
330    // - this target requires a writable block and either we're not
331    //   getting a writable block back or we have already snooped
332    //   another read request that will downgrade our writable block
333    //   to non-writable (Shared or Owned)
334    PacketPtr tgt_pkt = targets.front().pkt;
335    if (pkt->req->isCacheMaintenance() ||
336        tgt_pkt->req->isCacheMaintenance() ||
337        !deferredTargets.empty() ||
338        (inService &&
339         (hasPostInvalidate() ||
340          (pkt->needsWritable() &&
341           (!isPendingModified() || hasPostDowngrade() || isForward))))) {
342        // need to put on deferred list
343        if (inService && hasPostInvalidate())
344            replaceUpgrade(pkt);
345        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true,
346                            alloc_on_fill);
347    } else {
348        // No request outstanding, or still OK to append to
349        // outstanding request: append to regular target list.  Only
350        // mark pending if current request hasn't been issued yet
351        // (isn't in service).
352        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
353                    alloc_on_fill);
354    }
355}
356
357bool
358MSHR::handleSnoop(PacketPtr pkt, Counter _order)
359{
360    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
361
362    // when we snoop packets the needsWritable and isInvalidate flags
363    // should always be the same, however, this assumes that we never
364    // snoop writes as they are currently not marked as invalidations
365    panic_if((pkt->needsWritable() != pkt->isInvalidate()) &&
366             !pkt->req->isCacheMaintenance(),
367             "%s got snoop %s where needsWritable, "
368             "does not match isInvalidate", name(), pkt->print());
369
370    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
371        // Request has not been issued yet, or it's been issued
372        // locally but is buffered unissued at some downstream cache
373        // which is forwarding us this snoop.  Either way, the packet
374        // we're snooping logically precedes this MSHR's request, so
375        // the snoop has no impact on the MSHR, but must be processed
376        // in the standard way by the cache.  The only exception is
377        // that if we're an L2+ cache buffering an UpgradeReq from a
378        // higher-level cache, and the snoop is invalidating, then our
379        // buffered upgrades must be converted to read exclusives,
380        // since the upper-level cache no longer has a valid copy.
381        // That is, even though the upper-level cache got out on its
382        // local bus first, some other invalidating transaction
383        // reached the global bus before the upgrade did.
384        if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
385            targets.replaceUpgrades();
386            deferredTargets.replaceUpgrades();
387        }
388
389        return false;
390    }
391
392    // From here on down, the request issued by this MSHR logically
393    // precedes the request we're snooping.
394    if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
395        // snooped request still precedes the re-request we'll have to
396        // issue for deferred targets, if any...
397        deferredTargets.replaceUpgrades();
398    }
399
400    PacketPtr tgt_pkt = targets.front().pkt;
401    if (hasPostInvalidate() || tgt_pkt->req->isCacheInvalidate()) {
402        // a prior snoop has already appended an invalidation or a
403        // cache invalidation operation is in progress, so logically
404        // we don't have the block anymore; no need for further
405        // snooping.
406        return true;
407    }
408
409    if (isPendingModified() || pkt->isInvalidate()) {
410        // We need to save and replay the packet in two cases:
411        // 1. We're awaiting a writable copy (Modified or Exclusive),
412        //    so this MSHR is the orgering point, and we need to respond
413        //    after we receive data.
414        // 2. It's an invalidation (e.g., UpgradeReq), and we need
415        //    to forward the snoop up the hierarchy after the current
416        //    transaction completes.
417
418        // Start by determining if we will eventually respond or not,
419        // matching the conditions checked in Cache::handleSnoop
420        bool will_respond = isPendingModified() && pkt->needsResponse() &&
421                      !pkt->isClean();
422
423        // The packet we are snooping may be deleted by the time we
424        // actually process the target, and we consequently need to
425        // save a copy here. Clear flags and also allocate new data as
426        // the original packet data storage may have been deleted by
427        // the time we get to process this packet. In the cases where
428        // we are not responding after handling the snoop we also need
429        // to create a copy of the request to be on the safe side. In
430        // the latter case the cache is responsible for deleting both
431        // the packet and the request as part of handling the deferred
432        // snoop.
433        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
434            new Packet(std::make_shared<Request>(*pkt->req), pkt->cmd,
435                       blkSize, pkt->id);
436
437        if (will_respond) {
438            // we are the ordering point, and will consequently
439            // respond, and depending on whether the packet
440            // needsWritable or not we either pass a Shared line or a
441            // Modified line
442            pkt->setCacheResponding();
443
444            // inform the cache hierarchy that this cache had the line
445            // in the Modified state, even if the response is passed
446            // as Shared (and thus non-writable)
447            pkt->setResponderHadWritable();
448
449            // in the case of an uncacheable request there is no need
450            // to set the responderHadWritable flag, but since the
451            // recipient does not care there is no harm in doing so
452        }
453        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
454                    downstreamPending && targets.needsWritable, false);
455
456        if (pkt->needsWritable() || pkt->isInvalidate()) {
457            // This transaction will take away our pending copy
458            postInvalidate = true;
459        }
460
461        if (isPendingModified() && pkt->isClean()) {
462            pkt->setSatisfied();
463        }
464    }
465
466    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
467        // This transaction will get a read-shared copy, downgrading
468        // our copy if we had a writable one
469        postDowngrade = true;
470        // make sure that any downstream cache does not respond with a
471        // writable (and dirty) copy even if it has one, unless it was
472        // explicitly asked for one
473        pkt->setHasSharers();
474    }
475
476    return true;
477}
478
479MSHR::TargetList
480MSHR::extractServiceableTargets(PacketPtr pkt)
481{
482    TargetList ready_targets;
483    // If the downstream MSHR got an invalidation request then we only
484    // service the first of the FromCPU targets and any other
485    // non-FromCPU target. This way the remaining FromCPU targets
486    // issue a new request and get a fresh copy of the block and we
487    // avoid memory consistency violations.
488    if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
489        auto it = targets.begin();
490        assert((it->source == Target::FromCPU) ||
491               (it->source == Target::FromPrefetcher));
492        ready_targets.push_back(*it);
493        it = targets.erase(it);
494        while (it != targets.end()) {
495            if (it->source == Target::FromCPU) {
496                it++;
497            } else {
498                assert(it->source == Target::FromSnoop);
499                ready_targets.push_back(*it);
500                it = targets.erase(it);
501            }
502        }
503        ready_targets.populateFlags();
504    } else {
505        std::swap(ready_targets, targets);
506    }
507    targets.populateFlags();
508
509    return ready_targets;
510}
511
512bool
513MSHR::promoteDeferredTargets()
514{
515    if (targets.empty() && deferredTargets.empty()) {
516        // nothing to promote
517        return false;
518    }
519
520    // the deferred targets can be generally promoted unless they
521    // contain a cache maintenance request
522
523    // find the first target that is a cache maintenance request
524    auto it = std::find_if(deferredTargets.begin(), deferredTargets.end(),
525                           [](MSHR::Target &t) {
526                               return t.pkt->req->isCacheMaintenance();
527                           });
528    if (it == deferredTargets.begin()) {
529        // if the first deferred target is a cache maintenance packet
530        // then we can promote provided the targets list is empty and
531        // we can service it on its own
532        if (targets.empty()) {
533            targets.splice(targets.end(), deferredTargets, it);
534        }
535    } else {
536        // if a cache maintenance operation exists, we promote all the
537        // deferred targets that precede it, or all deferred targets
538        // otherwise
539        targets.splice(targets.end(), deferredTargets,
540                       deferredTargets.begin(), it);
541    }
542
543    deferredTargets.populateFlags();
544    targets.populateFlags();
545    order = targets.front().order;
546    readyTime = std::max(curTick(), targets.front().readyTime);
547
548    return true;
549}
550
551
552void
553MSHR::promoteWritable()
554{
555    if (deferredTargets.needsWritable &&
556        !(hasPostInvalidate() || hasPostDowngrade())) {
557        // We got a writable response, but we have deferred targets
558        // which are waiting to request a writable copy (not because
559        // of a pending invalidate).  This can happen if the original
560        // request was for a read-only block, but we got a writable
561        // response anyway. Since we got the writable copy there's no
562        // need to defer the targets, so move them up to the regular
563        // target list.
564        assert(!targets.needsWritable);
565        targets.needsWritable = true;
566        // if any of the deferred targets were upper-level cache
567        // requests marked downstreamPending, need to clear that
568        assert(!downstreamPending);  // not pending here anymore
569
570        auto last_it = std::find_if(
571            deferredTargets.begin(), deferredTargets.end(),
572            [](MSHR::Target &t) {
573                assert(t.source == Target::FromCPU);
574                return t.pkt->req->isCacheInvalidate();
575            });
576        deferredTargets.clearDownstreamPending(deferredTargets.begin(),
577                                               last_it);
578        targets.splice(targets.end(), deferredTargets,
579                       deferredTargets.begin(), last_it);
580        // We need to update the flags for the target lists after the
581        // modifications
582        deferredTargets.populateFlags();
583    }
584}
585
586
587bool
588MSHR::checkFunctional(PacketPtr pkt)
589{
590    // For printing, we treat the MSHR as a whole as single entity.
591    // For other requests, we iterate over the individual targets
592    // since that's where the actual data lies.
593    if (pkt->isPrint()) {
594        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
595        return false;
596    } else {
597        return (targets.checkFunctional(pkt) ||
598                deferredTargets.checkFunctional(pkt));
599    }
600}
601
602bool
603MSHR::sendPacket(BaseCache &cache)
604{
605    return cache.sendMSHRQueuePacket(this);
606}
607
608void
609MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
610{
611    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
612             prefix, blkAddr, blkAddr + blkSize - 1,
613             isSecure ? "s" : "ns",
614             isForward ? "Forward" : "",
615             allocOnFill() ? "AllocOnFill" : "",
616             needsWritable() ? "Wrtbl" : "",
617             _isUncacheable ? "Unc" : "",
618             inService ? "InSvc" : "",
619             downstreamPending ? "DwnPend" : "",
620             postInvalidate ? "PostInv" : "",
621             postDowngrade ? "PostDowngr" : "",
622             hasFromCache() ? "HasFromCache" : "");
623
624    if (!targets.empty()) {
625        ccprintf(os, "%s  Targets:\n", prefix);
626        targets.print(os, verbosity, prefix + "    ");
627    }
628    if (!deferredTargets.empty()) {
629        ccprintf(os, "%s  Deferred Targets:\n", prefix);
630        deferredTargets.print(os, verbosity, prefix + "      ");
631    }
632}
633
634std::string
635MSHR::print() const
636{
637    std::ostringstream str;
638    print(str);
639    return str.str();
640}
641