mshr.cc revision 11278:18411ccc4f3c
19157Sandreas.hansson@arm.com/* 29793Sakash.bagdia@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited 39157Sandreas.hansson@arm.com * All rights reserved. 49157Sandreas.hansson@arm.com * 59157Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69157Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79157Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89157Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99157Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109157Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119157Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129157Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139157Sandreas.hansson@arm.com * 149157Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 159157Sandreas.hansson@arm.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 169157Sandreas.hansson@arm.com * All rights reserved. 179157Sandreas.hansson@arm.com * 189157Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 199157Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 209157Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 219157Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 229157Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 239157Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 249157Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 259157Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 269157Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 279157Sandreas.hansson@arm.com * this software without specific prior written permission. 289157Sandreas.hansson@arm.com * 299157Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 309157Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 319157Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 329157Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 339157Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349157Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359157Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369157Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379157Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389157Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399157Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409157Sandreas.hansson@arm.com * 419157Sandreas.hansson@arm.com * Authors: Erik Hallnor 429157Sandreas.hansson@arm.com * Dave Greene 439157Sandreas.hansson@arm.com */ 449157Sandreas.hansson@arm.com 459157Sandreas.hansson@arm.com/** 469157Sandreas.hansson@arm.com * @file 479157Sandreas.hansson@arm.com * Miss Status and Handling Register (MSHR) definitions. 489157Sandreas.hansson@arm.com */ 499418Sandreas.hansson@arm.com 509157Sandreas.hansson@arm.com#include <algorithm> 519356Snilay@cs.wisc.edu#include <cassert> 529793Sakash.bagdia@arm.com#include <string> 539157Sandreas.hansson@arm.com#include <vector> 549157Sandreas.hansson@arm.com 559157Sandreas.hansson@arm.com#include "base/misc.hh" 569157Sandreas.hansson@arm.com#include "base/types.hh" 579157Sandreas.hansson@arm.com#include "debug/Cache.hh" 589157Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 599157Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 609157Sandreas.hansson@arm.com#include "sim/core.hh" 619157Sandreas.hansson@arm.com 629157Sandreas.hansson@arm.comusing namespace std; 639157Sandreas.hansson@arm.com 649179Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false), 659179Sandreas.hansson@arm.com pendingDirty(false), 669179Sandreas.hansson@arm.com postInvalidate(false), postDowngrade(false), 679179Sandreas.hansson@arm.com queue(NULL), order(0), blkAddr(0), 689179Sandreas.hansson@arm.com blkSize(0), isSecure(false), inService(false), 699179Sandreas.hansson@arm.com isForward(false), allocOnFill(false), 709180Sandreas.hansson@arm.com data(NULL) 719179Sandreas.hansson@arm.com{ 729157Sandreas.hansson@arm.com} 739157Sandreas.hansson@arm.com 749157Sandreas.hansson@arm.com 759157Sandreas.hansson@arm.comMSHR::TargetList::TargetList() 769157Sandreas.hansson@arm.com : needsExclusive(false), hasUpgrade(false) 779157Sandreas.hansson@arm.com{} 789157Sandreas.hansson@arm.com 799179Sandreas.hansson@arm.com 809179Sandreas.hansson@arm.cominline void 819179Sandreas.hansson@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 829179Sandreas.hansson@arm.com Counter order, Target::Source source, bool markPending) 839179Sandreas.hansson@arm.com{ 849179Sandreas.hansson@arm.com if (source != Target::FromSnoop) { 859179Sandreas.hansson@arm.com if (pkt->needsExclusive()) { 869179Sandreas.hansson@arm.com needsExclusive = true; 879179Sandreas.hansson@arm.com } 889179Sandreas.hansson@arm.com 899179Sandreas.hansson@arm.com // StoreCondReq is effectively an upgrade if it's in an MSHR 909179Sandreas.hansson@arm.com // since it would have been failed already if we didn't have a 919179Sandreas.hansson@arm.com // read-only copy 929793Sakash.bagdia@arm.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 939179Sandreas.hansson@arm.com hasUpgrade = true; 949179Sandreas.hansson@arm.com } 959179Sandreas.hansson@arm.com } 969179Sandreas.hansson@arm.com 979179Sandreas.hansson@arm.com if (markPending) { 989179Sandreas.hansson@arm.com // Iterate over the SenderState stack and see if we find 999179Sandreas.hansson@arm.com // an MSHR entry. If we do, set the downstreamPending 1009179Sandreas.hansson@arm.com // flag. Otherwise, do nothing. 1019179Sandreas.hansson@arm.com MSHR *mshr = pkt->findNextSenderState<MSHR>(); 1029793Sakash.bagdia@arm.com if (mshr != NULL) { 1039179Sandreas.hansson@arm.com assert(!mshr->downstreamPending); 1049793Sakash.bagdia@arm.com mshr->downstreamPending = true; 1059179Sandreas.hansson@arm.com } else { 1069179Sandreas.hansson@arm.com // No need to clear downstreamPending later 1079793Sakash.bagdia@arm.com markPending = false; 1089793Sakash.bagdia@arm.com } 1099793Sakash.bagdia@arm.com } 1109793Sakash.bagdia@arm.com 1119157Sandreas.hansson@arm.com emplace_back(pkt, readyTime, order, source, markPending); 1129545Sandreas.hansson@arm.com} 1139545Sandreas.hansson@arm.com 1149157Sandreas.hansson@arm.com 1159793Sakash.bagdia@arm.comstatic void 1169157Sandreas.hansson@arm.comreplaceUpgrade(PacketPtr pkt) 1179157Sandreas.hansson@arm.com{ 1189179Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::UpgradeReq) { 1199793Sakash.bagdia@arm.com pkt->cmd = MemCmd::ReadExReq; 1209418Sandreas.hansson@arm.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1219418Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1229157Sandreas.hansson@arm.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1239157Sandreas.hansson@arm.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1249157Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1259157Sandreas.hansson@arm.com pkt->cmd = MemCmd::StoreCondFailReq; 1269157Sandreas.hansson@arm.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1279157Sandreas.hansson@arm.com } 1289296Snilay@cs.wisc.edu} 1299296Snilay@cs.wisc.edu 1309296Snilay@cs.wisc.edu 1319296Snilay@cs.wisc.eduvoid 1329296Snilay@cs.wisc.eduMSHR::TargetList::replaceUpgrades() 1339296Snilay@cs.wisc.edu{ 1349296Snilay@cs.wisc.edu if (!hasUpgrade) 1359793Sakash.bagdia@arm.com return; 1369296Snilay@cs.wisc.edu 1379793Sakash.bagdia@arm.com for (auto& t : *this) { 1389296Snilay@cs.wisc.edu replaceUpgrade(t.pkt); 1399296Snilay@cs.wisc.edu } 1409157Sandreas.hansson@arm.com 1419157Sandreas.hansson@arm.com hasUpgrade = false; 1429157Sandreas.hansson@arm.com} 1439179Sandreas.hansson@arm.com 1449179Sandreas.hansson@arm.com 1459179Sandreas.hansson@arm.comvoid 1469179Sandreas.hansson@arm.comMSHR::TargetList::clearDownstreamPending() 1479179Sandreas.hansson@arm.com{ 1489179Sandreas.hansson@arm.com for (auto& t : *this) { 1499179Sandreas.hansson@arm.com if (t.markedPending) { 1509179Sandreas.hansson@arm.com // Iterate over the SenderState stack and see if we find 1519180Sandreas.hansson@arm.com // an MSHR entry. If we find one, clear the 1529179Sandreas.hansson@arm.com // downstreamPending flag by calling 1539179Sandreas.hansson@arm.com // clearDownstreamPending(). This recursively clears the 1549179Sandreas.hansson@arm.com // downstreamPending flag in all caches this packet has 1559179Sandreas.hansson@arm.com // passed through. 1569179Sandreas.hansson@arm.com MSHR *mshr = t.pkt->findNextSenderState<MSHR>(); 1579793Sakash.bagdia@arm.com if (mshr != NULL) { 1589179Sandreas.hansson@arm.com mshr->clearDownstreamPending(); 1599179Sandreas.hansson@arm.com } 1609179Sandreas.hansson@arm.com } 1619179Sandreas.hansson@arm.com } 1629179Sandreas.hansson@arm.com} 1639179Sandreas.hansson@arm.com 1649180Sandreas.hansson@arm.com 1659179Sandreas.hansson@arm.combool 1669180Sandreas.hansson@arm.comMSHR::TargetList::checkFunctional(PacketPtr pkt) 1679179Sandreas.hansson@arm.com{ 1689179Sandreas.hansson@arm.com for (auto& t : *this) { 1699179Sandreas.hansson@arm.com if (pkt->checkFunctional(t.pkt)) { 1709179Sandreas.hansson@arm.com return true; 1719179Sandreas.hansson@arm.com } 1729179Sandreas.hansson@arm.com } 1739179Sandreas.hansson@arm.com 1749179Sandreas.hansson@arm.com return false; 1759648Sdam.sunwoo@arm.com} 1769648Sdam.sunwoo@arm.com 1779648Sdam.sunwoo@arm.com 1789157Sandreas.hansson@arm.comvoid 1799157Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity, 1809157Sandreas.hansson@arm.com const std::string &prefix) const 1819157Sandreas.hansson@arm.com{ 1829648Sdam.sunwoo@arm.com for (auto& t : *this) { 1839157Sandreas.hansson@arm.com const char *s; 1849793Sakash.bagdia@arm.com switch (t.source) { 1859793Sakash.bagdia@arm.com case Target::FromCPU: 1869793Sakash.bagdia@arm.com s = "FromCPU"; 1879793Sakash.bagdia@arm.com break; 1889157Sandreas.hansson@arm.com case Target::FromSnoop: 1899793Sakash.bagdia@arm.com s = "FromSnoop"; 1909793Sakash.bagdia@arm.com break; 1919793Sakash.bagdia@arm.com case Target::FromPrefetcher: 1929793Sakash.bagdia@arm.com s = "FromPrefetcher"; 1939157Sandreas.hansson@arm.com break; 1949550Sandreas.hansson@arm.com default: 1959793Sakash.bagdia@arm.com s = ""; 1969157Sandreas.hansson@arm.com break; 1979157Sandreas.hansson@arm.com } 1989157Sandreas.hansson@arm.com ccprintf(os, "%s%s: ", prefix, s); 1999157Sandreas.hansson@arm.com t.pkt->print(os, verbosity, ""); 200 } 201} 202 203 204void 205MSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 206 Tick when_ready, Counter _order, bool alloc_on_fill) 207{ 208 blkAddr = blk_addr; 209 blkSize = blk_size; 210 isSecure = target->isSecure(); 211 readyTime = when_ready; 212 order = _order; 213 assert(target); 214 isForward = false; 215 allocOnFill = alloc_on_fill; 216 _isUncacheable = target->req->isUncacheable(); 217 inService = false; 218 downstreamPending = false; 219 assert(targets.isReset()); 220 // Don't know of a case where we would allocate a new MSHR for a 221 // snoop (mem-side request), so set source according to request here 222 Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 223 Target::FromPrefetcher : Target::FromCPU; 224 targets.add(target, when_ready, _order, source, true); 225 assert(deferredTargets.isReset()); 226 data = NULL; 227} 228 229 230void 231MSHR::clearDownstreamPending() 232{ 233 assert(downstreamPending); 234 downstreamPending = false; 235 // recursively clear flag on any MSHRs we will be forwarding 236 // responses to 237 targets.clearDownstreamPending(); 238} 239 240bool 241MSHR::markInService(bool pending_dirty_resp) 242{ 243 assert(!inService); 244 if (isForwardNoResponse()) { 245 // we just forwarded the request packet & don't expect a 246 // response, so get rid of it 247 assert(getNumTargets() == 1); 248 popTarget(); 249 return true; 250 } 251 252 inService = true; 253 pendingDirty = targets.needsExclusive || pending_dirty_resp; 254 postInvalidate = postDowngrade = false; 255 256 if (!downstreamPending) { 257 // let upstream caches know that the request has made it to a 258 // level where it's going to get a response 259 targets.clearDownstreamPending(); 260 } 261 return false; 262} 263 264 265void 266MSHR::deallocate() 267{ 268 assert(targets.empty()); 269 targets.resetFlags(); 270 assert(deferredTargets.isReset()); 271 inService = false; 272} 273 274/* 275 * Adds a target to an MSHR 276 */ 277void 278MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order, 279 bool alloc_on_fill) 280{ 281 // assume we'd never issue a prefetch when we've got an 282 // outstanding miss 283 assert(pkt->cmd != MemCmd::HardPFReq); 284 285 // uncacheable accesses always allocate a new MSHR, and cacheable 286 // accesses ignore any uncacheable MSHRs, thus we should never 287 // have targets addded if originally allocated uncacheable 288 assert(!_isUncacheable); 289 290 // potentially re-evaluate whether we should allocate on a fill or 291 // not 292 allocOnFill = allocOnFill || alloc_on_fill; 293 294 // if there's a request already in service for this MSHR, we will 295 // have to defer the new target until after the response if any of 296 // the following are true: 297 // - there are other targets already deferred 298 // - there's a pending invalidate to be applied after the response 299 // comes back (but before this target is processed) 300 // - this target requires an exclusive block and either we're not 301 // getting an exclusive block back or we have already snooped 302 // another read request that will downgrade our exclusive block 303 // to shared 304 if (inService && 305 (!deferredTargets.empty() || hasPostInvalidate() || 306 (pkt->needsExclusive() && 307 (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 308 // need to put on deferred list 309 if (hasPostInvalidate()) 310 replaceUpgrade(pkt); 311 deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true); 312 } else { 313 // No request outstanding, or still OK to append to 314 // outstanding request: append to regular target list. Only 315 // mark pending if current request hasn't been issued yet 316 // (isn't in service). 317 targets.add(pkt, whenReady, _order, Target::FromCPU, !inService); 318 } 319} 320 321bool 322MSHR::handleSnoop(PacketPtr pkt, Counter _order) 323{ 324 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 325 pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 326 if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 327 // Request has not been issued yet, or it's been issued 328 // locally but is buffered unissued at some downstream cache 329 // which is forwarding us this snoop. Either way, the packet 330 // we're snooping logically precedes this MSHR's request, so 331 // the snoop has no impact on the MSHR, but must be processed 332 // in the standard way by the cache. The only exception is 333 // that if we're an L2+ cache buffering an UpgradeReq from a 334 // higher-level cache, and the snoop is invalidating, then our 335 // buffered upgrades must be converted to read exclusives, 336 // since the upper-level cache no longer has a valid copy. 337 // That is, even though the upper-level cache got out on its 338 // local bus first, some other invalidating transaction 339 // reached the global bus before the upgrade did. 340 if (pkt->needsExclusive()) { 341 targets.replaceUpgrades(); 342 deferredTargets.replaceUpgrades(); 343 } 344 345 return false; 346 } 347 348 // From here on down, the request issued by this MSHR logically 349 // precedes the request we're snooping. 350 if (pkt->needsExclusive()) { 351 // snooped request still precedes the re-request we'll have to 352 // issue for deferred targets, if any... 353 deferredTargets.replaceUpgrades(); 354 } 355 356 if (hasPostInvalidate()) { 357 // a prior snoop has already appended an invalidation, so 358 // logically we don't have the block anymore; no need for 359 // further snooping. 360 return true; 361 } 362 363 if (isPendingDirty() || pkt->isInvalidate()) { 364 // We need to save and replay the packet in two cases: 365 // 1. We're awaiting an exclusive copy, so ownership is pending, 366 // and we need to deal with the snoop after we receive data. 367 // 2. It's an invalidation (e.g., UpgradeReq), and we need 368 // to forward the snoop up the hierarchy after the current 369 // transaction completes. 370 371 // Start by determining if we will eventually respond or not, 372 // matching the conditions checked in Cache::handleSnoop 373 bool will_respond = isPendingDirty() && pkt->needsResponse() && 374 pkt->cmd != MemCmd::InvalidateReq; 375 376 // The packet we are snooping may be deleted by the time we 377 // actually process the target, and we consequently need to 378 // save a copy here. Clear flags and also allocate new data as 379 // the original packet data storage may have been deleted by 380 // the time we get to process this packet. In the cases where 381 // we are not responding after handling the snoop we also need 382 // to create a copy of the request to be on the safe side. In 383 // the latter case the cache is responsible for deleting both 384 // the packet and the request as part of handling the deferred 385 // snoop. 386 PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) : 387 new Packet(new Request(*pkt->req), pkt->cmd); 388 389 if (isPendingDirty()) { 390 // The new packet will need to get the response from the 391 // MSHR already queued up here 392 pkt->assertMemInhibit(); 393 // in the case of an uncacheable request there is no need 394 // to set the exclusive flag, but since the recipient does 395 // not care there is no harm in doing so 396 pkt->setSupplyExclusive(); 397 } 398 targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 399 downstreamPending && targets.needsExclusive); 400 401 if (pkt->needsExclusive()) { 402 // This transaction will take away our pending copy 403 postInvalidate = true; 404 } 405 } 406 407 if (!pkt->needsExclusive() && !pkt->req->isUncacheable()) { 408 // This transaction will get a read-shared copy, downgrading 409 // our copy if we had an exclusive one 410 postDowngrade = true; 411 pkt->assertShared(); 412 } 413 414 return true; 415} 416 417 418bool 419MSHR::promoteDeferredTargets() 420{ 421 assert(targets.empty()); 422 if (deferredTargets.empty()) { 423 return false; 424 } 425 426 // swap targets & deferredTargets lists 427 std::swap(targets, deferredTargets); 428 429 // clear deferredTargets flags 430 deferredTargets.resetFlags(); 431 432 order = targets.front().order; 433 readyTime = std::max(curTick(), targets.front().readyTime); 434 435 return true; 436} 437 438 439void 440MSHR::promoteExclusive() 441{ 442 if (deferredTargets.needsExclusive && 443 !(hasPostInvalidate() || hasPostDowngrade())) { 444 // We got an exclusive response, but we have deferred targets 445 // which are waiting to request an exclusive copy (not because 446 // of a pending invalidate). This can happen if the original 447 // request was for a read-only (non-exclusive) block, but we 448 // got an exclusive copy anyway because of the E part of the 449 // MOESI/MESI protocol. Since we got the exclusive copy 450 // there's no need to defer the targets, so move them up to 451 // the regular target list. 452 assert(!targets.needsExclusive); 453 targets.needsExclusive = true; 454 // if any of the deferred targets were upper-level cache 455 // requests marked downstreamPending, need to clear that 456 assert(!downstreamPending); // not pending here anymore 457 deferredTargets.clearDownstreamPending(); 458 // this clears out deferredTargets too 459 targets.splice(targets.end(), deferredTargets); 460 deferredTargets.resetFlags(); 461 } 462} 463 464 465bool 466MSHR::checkFunctional(PacketPtr pkt) 467{ 468 // For printing, we treat the MSHR as a whole as single entity. 469 // For other requests, we iterate over the individual targets 470 // since that's where the actual data lies. 471 if (pkt->isPrint()) { 472 pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL); 473 return false; 474 } else { 475 return (targets.checkFunctional(pkt) || 476 deferredTargets.checkFunctional(pkt)); 477 } 478} 479 480 481void 482MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 483{ 484 ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n", 485 prefix, blkAddr, blkAddr + blkSize - 1, 486 isSecure ? "s" : "ns", 487 isForward ? "Forward" : "", 488 allocOnFill ? "AllocOnFill" : "", 489 isForwardNoResponse() ? "ForwNoResp" : "", 490 needsExclusive() ? "Excl" : "", 491 _isUncacheable ? "Unc" : "", 492 inService ? "InSvc" : "", 493 downstreamPending ? "DwnPend" : "", 494 hasPostInvalidate() ? "PostInv" : "", 495 hasPostDowngrade() ? "PostDowngr" : ""); 496 497 ccprintf(os, "%s Targets:\n", prefix); 498 targets.print(os, verbosity, prefix + " "); 499 if (!deferredTargets.empty()) { 500 ccprintf(os, "%s Deferred Targets:\n", prefix); 501 deferredTargets.print(os, verbosity, prefix + " "); 502 } 503} 504 505std::string 506MSHR::print() const 507{ 508 ostringstream str; 509 print(str); 510 return str.str(); 511} 512