mshr.cc revision 10922:5ee72f4b2931
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2012-2013, 2015 ARM Limited 35086Sgblack@eecs.umich.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 65086Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 75086Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 85086Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 95086Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 105086Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 115086Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 125086Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 135086Sgblack@eecs.umich.edu * 145086Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 155086Sgblack@eecs.umich.edu * Copyright (c) 2010 Advanced Micro Devices, Inc. 165086Sgblack@eecs.umich.edu * All rights reserved. 175086Sgblack@eecs.umich.edu * 185086Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195086Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 205086Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215086Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225086Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235086Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245086Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255086Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275086Sgblack@eecs.umich.edu * this software without specific prior written permission. 285086Sgblack@eecs.umich.edu * 295086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405086Sgblack@eecs.umich.edu * 415086Sgblack@eecs.umich.edu * Authors: Erik Hallnor 425086Sgblack@eecs.umich.edu * Dave Greene 435086Sgblack@eecs.umich.edu */ 445086Sgblack@eecs.umich.edu 455086Sgblack@eecs.umich.edu/** 465086Sgblack@eecs.umich.edu * @file 475086Sgblack@eecs.umich.edu * Miss Status and Handling Register (MSHR) definitions. 485086Sgblack@eecs.umich.edu */ 495086Sgblack@eecs.umich.edu 505086Sgblack@eecs.umich.edu#include <algorithm> 515086Sgblack@eecs.umich.edu#include <cassert> 525086Sgblack@eecs.umich.edu#include <string> 535086Sgblack@eecs.umich.edu#include <vector> 545086Sgblack@eecs.umich.edu 555086Sgblack@eecs.umich.edu#include "base/misc.hh" 565086Sgblack@eecs.umich.edu#include "base/types.hh" 575086Sgblack@eecs.umich.edu#include "debug/Cache.hh" 585647Sgblack@eecs.umich.edu#include "mem/cache/cache.hh" 595647Sgblack@eecs.umich.edu#include "mem/cache/mshr.hh" 605647Sgblack@eecs.umich.edu#include "sim/core.hh" 615647Sgblack@eecs.umich.edu 625647Sgblack@eecs.umich.eduusing namespace std; 635135Sgblack@eecs.umich.edu 645135Sgblack@eecs.umich.eduMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false), 655135Sgblack@eecs.umich.edu pendingDirty(false), 665086Sgblack@eecs.umich.edu postInvalidate(false), postDowngrade(false), 675135Sgblack@eecs.umich.edu queue(NULL), order(0), blkAddr(0), 685647Sgblack@eecs.umich.edu blkSize(0), isSecure(false), inService(false), 695234Sgblack@eecs.umich.edu isForward(false), threadNum(InvalidThreadID), data(NULL) 705086Sgblack@eecs.umich.edu{ 715086Sgblack@eecs.umich.edu} 725086Sgblack@eecs.umich.edu 735086Sgblack@eecs.umich.edu 745086Sgblack@eecs.umich.eduMSHR::TargetList::TargetList() 755086Sgblack@eecs.umich.edu : needsExclusive(false), hasUpgrade(false) 765086Sgblack@eecs.umich.edu{} 775086Sgblack@eecs.umich.edu 785086Sgblack@eecs.umich.edu 795086Sgblack@eecs.umich.eduinline void 805086Sgblack@eecs.umich.eduMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 815135Sgblack@eecs.umich.edu Counter order, Target::Source source, bool markPending) 825135Sgblack@eecs.umich.edu{ 835135Sgblack@eecs.umich.edu if (source != Target::FromSnoop) { 845135Sgblack@eecs.umich.edu if (pkt->needsExclusive()) { 856048Sgblack@eecs.umich.edu needsExclusive = true; 866048Sgblack@eecs.umich.edu } 876048Sgblack@eecs.umich.edu 886048Sgblack@eecs.umich.edu // StoreCondReq is effectively an upgrade if it's in an MSHR 896048Sgblack@eecs.umich.edu // since it would have been failed already if we didn't have a 906048Sgblack@eecs.umich.edu // read-only copy 916048Sgblack@eecs.umich.edu if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 926048Sgblack@eecs.umich.edu hasUpgrade = true; 935135Sgblack@eecs.umich.edu } 945135Sgblack@eecs.umich.edu } 955135Sgblack@eecs.umich.edu 965135Sgblack@eecs.umich.edu if (markPending) { 975135Sgblack@eecs.umich.edu // Iterate over the SenderState stack and see if we find 985135Sgblack@eecs.umich.edu // an MSHR entry. If we do, set the downstreamPending 995135Sgblack@eecs.umich.edu // flag. Otherwise, do nothing. 1005135Sgblack@eecs.umich.edu MSHR *mshr = pkt->findNextSenderState<MSHR>(); 1015135Sgblack@eecs.umich.edu if (mshr != NULL) { 1025135Sgblack@eecs.umich.edu assert(!mshr->downstreamPending); 1035135Sgblack@eecs.umich.edu mshr->downstreamPending = true; 1045135Sgblack@eecs.umich.edu } 1055135Sgblack@eecs.umich.edu } 1065135Sgblack@eecs.umich.edu 1075135Sgblack@eecs.umich.edu emplace_back(pkt, readyTime, order, source, markPending); 1085135Sgblack@eecs.umich.edu} 1095135Sgblack@eecs.umich.edu 1105264Sgblack@eecs.umich.edu 1115135Sgblack@eecs.umich.edustatic void 1125135Sgblack@eecs.umich.edureplaceUpgrade(PacketPtr pkt) 1135135Sgblack@eecs.umich.edu{ 1145135Sgblack@eecs.umich.edu if (pkt->cmd == MemCmd::UpgradeReq) { 1155141Sgblack@eecs.umich.edu pkt->cmd = MemCmd::ReadExReq; 1165141Sgblack@eecs.umich.edu DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1175141Sgblack@eecs.umich.edu } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1185141Sgblack@eecs.umich.edu pkt->cmd = MemCmd::SCUpgradeFailReq; 1195141Sgblack@eecs.umich.edu DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1205141Sgblack@eecs.umich.edu } else if (pkt->cmd == MemCmd::StoreCondReq) { 1215141Sgblack@eecs.umich.edu pkt->cmd = MemCmd::StoreCondFailReq; 1225141Sgblack@eecs.umich.edu DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1235141Sgblack@eecs.umich.edu } 1245182Sgblack@eecs.umich.edu} 1255141Sgblack@eecs.umich.edu 1265141Sgblack@eecs.umich.edu 1275141Sgblack@eecs.umich.eduvoid 1285141Sgblack@eecs.umich.eduMSHR::TargetList::replaceUpgrades() 1295141Sgblack@eecs.umich.edu{ 1305141Sgblack@eecs.umich.edu if (!hasUpgrade) 1315135Sgblack@eecs.umich.edu return; 1325141Sgblack@eecs.umich.edu 1335141Sgblack@eecs.umich.edu for (auto& t : *this) { 1345141Sgblack@eecs.umich.edu replaceUpgrade(t.pkt); 1355141Sgblack@eecs.umich.edu } 1365141Sgblack@eecs.umich.edu 1375141Sgblack@eecs.umich.edu hasUpgrade = false; 1385141Sgblack@eecs.umich.edu} 1395141Sgblack@eecs.umich.edu 1405141Sgblack@eecs.umich.edu 1415141Sgblack@eecs.umich.eduvoid 1425141Sgblack@eecs.umich.eduMSHR::TargetList::clearDownstreamPending() 1435141Sgblack@eecs.umich.edu{ 1445135Sgblack@eecs.umich.edu for (auto& t : *this) { 1455141Sgblack@eecs.umich.edu if (t.markedPending) { 1465141Sgblack@eecs.umich.edu // Iterate over the SenderState stack and see if we find 1475135Sgblack@eecs.umich.edu // an MSHR entry. If we find one, clear the 1485141Sgblack@eecs.umich.edu // downstreamPending flag by calling 1495141Sgblack@eecs.umich.edu // clearDownstreamPending(). This recursively clears the 1505141Sgblack@eecs.umich.edu // downstreamPending flag in all caches this packet has 1515141Sgblack@eecs.umich.edu // passed through. 1525135Sgblack@eecs.umich.edu MSHR *mshr = t.pkt->findNextSenderState<MSHR>(); 1535141Sgblack@eecs.umich.edu if (mshr != NULL) { 1545141Sgblack@eecs.umich.edu mshr->clearDownstreamPending(); 1555141Sgblack@eecs.umich.edu } 1565141Sgblack@eecs.umich.edu } 1575141Sgblack@eecs.umich.edu } 1585141Sgblack@eecs.umich.edu} 1595141Sgblack@eecs.umich.edu 1605141Sgblack@eecs.umich.edu 1615141Sgblack@eecs.umich.edubool 1625141Sgblack@eecs.umich.eduMSHR::TargetList::checkFunctional(PacketPtr pkt) 1635141Sgblack@eecs.umich.edu{ 1645141Sgblack@eecs.umich.edu for (auto& t : *this) { 1655264Sgblack@eecs.umich.edu if (pkt->checkFunctional(t.pkt)) { 1665141Sgblack@eecs.umich.edu return true; 1675141Sgblack@eecs.umich.edu } 1685141Sgblack@eecs.umich.edu } 1695141Sgblack@eecs.umich.edu 1705141Sgblack@eecs.umich.edu return false; 1715141Sgblack@eecs.umich.edu} 1725141Sgblack@eecs.umich.edu 1735141Sgblack@eecs.umich.edu 1745141Sgblack@eecs.umich.eduvoid 1755141Sgblack@eecs.umich.eduMSHR::TargetList::print(std::ostream &os, int verbosity, 1765141Sgblack@eecs.umich.edu const std::string &prefix) const 1775141Sgblack@eecs.umich.edu{ 1785141Sgblack@eecs.umich.edu for (auto& t : *this) { 1795141Sgblack@eecs.umich.edu const char *s; 1805141Sgblack@eecs.umich.edu switch (t.source) { 1815141Sgblack@eecs.umich.edu case Target::FromCPU: 1825141Sgblack@eecs.umich.edu s = "FromCPU"; 1835135Sgblack@eecs.umich.edu break; 1845135Sgblack@eecs.umich.edu case Target::FromSnoop: 1855135Sgblack@eecs.umich.edu s = "FromSnoop"; 1865360Sgblack@eecs.umich.edu break; 1875360Sgblack@eecs.umich.edu case Target::FromPrefetcher: 1885360Sgblack@eecs.umich.edu s = "FromPrefetcher"; 1895360Sgblack@eecs.umich.edu break; 1905360Sgblack@eecs.umich.edu default: 1915360Sgblack@eecs.umich.edu s = ""; 1925647Sgblack@eecs.umich.edu break; 1935647Sgblack@eecs.umich.edu } 1945647Sgblack@eecs.umich.edu ccprintf(os, "%s%s: ", prefix, s); 1955360Sgblack@eecs.umich.edu t.pkt->print(os, verbosity, ""); 1965647Sgblack@eecs.umich.edu } 1975647Sgblack@eecs.umich.edu} 1985647Sgblack@eecs.umich.edu 1995648Sgblack@eecs.umich.edu 2005648Sgblack@eecs.umich.eduvoid 2015360Sgblack@eecs.umich.eduMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 2025141Sgblack@eecs.umich.edu Tick when_ready, Counter _order) 2035141Sgblack@eecs.umich.edu{ 2045141Sgblack@eecs.umich.edu blkAddr = blk_addr; 2055141Sgblack@eecs.umich.edu blkSize = blk_size; 2065141Sgblack@eecs.umich.edu isSecure = target->isSecure(); 2075141Sgblack@eecs.umich.edu readyTime = when_ready; 2085135Sgblack@eecs.umich.edu order = _order; 2095135Sgblack@eecs.umich.edu assert(target); 2105135Sgblack@eecs.umich.edu isForward = false; 2115135Sgblack@eecs.umich.edu _isUncacheable = target->req->isUncacheable(); 2125135Sgblack@eecs.umich.edu inService = false; 2135135Sgblack@eecs.umich.edu downstreamPending = false; 2146042Sgblack@eecs.umich.edu threadNum = 0; 2155135Sgblack@eecs.umich.edu assert(targets.isReset()); 2165135Sgblack@eecs.umich.edu // Don't know of a case where we would allocate a new MSHR for a 2175135Sgblack@eecs.umich.edu // snoop (mem-side request), so set source according to request here 2185135Sgblack@eecs.umich.edu Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2195135Sgblack@eecs.umich.edu Target::FromPrefetcher : Target::FromCPU; 2205135Sgblack@eecs.umich.edu targets.add(target, when_ready, _order, source, true); 2216042Sgblack@eecs.umich.edu assert(deferredTargets.isReset()); 2225135Sgblack@eecs.umich.edu data = NULL; 2236042Sgblack@eecs.umich.edu} 2246042Sgblack@eecs.umich.edu 2256042Sgblack@eecs.umich.edu 2265135Sgblack@eecs.umich.eduvoid 2275135Sgblack@eecs.umich.eduMSHR::clearDownstreamPending() 2285086Sgblack@eecs.umich.edu{ 229 assert(downstreamPending); 230 downstreamPending = false; 231 // recursively clear flag on any MSHRs we will be forwarding 232 // responses to 233 targets.clearDownstreamPending(); 234} 235 236bool 237MSHR::markInService(bool pending_dirty_resp) 238{ 239 assert(!inService); 240 if (isForwardNoResponse()) { 241 // we just forwarded the request packet & don't expect a 242 // response, so get rid of it 243 assert(getNumTargets() == 1); 244 popTarget(); 245 return true; 246 } 247 248 inService = true; 249 pendingDirty = targets.needsExclusive || pending_dirty_resp; 250 postInvalidate = postDowngrade = false; 251 252 if (!downstreamPending) { 253 // let upstream caches know that the request has made it to a 254 // level where it's going to get a response 255 targets.clearDownstreamPending(); 256 } 257 return false; 258} 259 260 261void 262MSHR::deallocate() 263{ 264 assert(targets.empty()); 265 targets.resetFlags(); 266 assert(deferredTargets.isReset()); 267 inService = false; 268} 269 270/* 271 * Adds a target to an MSHR 272 */ 273void 274MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order) 275{ 276 // assume we'd never issue a prefetch when we've got an 277 // outstanding miss 278 assert(pkt->cmd != MemCmd::HardPFReq); 279 280 // uncacheable accesses always allocate a new MSHR, and cacheable 281 // accesses ignore any uncacheable MSHRs, thus we should never 282 // have targets addded if originally allocated uncacheable 283 assert(!_isUncacheable); 284 285 // if there's a request already in service for this MSHR, we will 286 // have to defer the new target until after the response if any of 287 // the following are true: 288 // - there are other targets already deferred 289 // - there's a pending invalidate to be applied after the response 290 // comes back (but before this target is processed) 291 // - this target requires an exclusive block and either we're not 292 // getting an exclusive block back or we have already snooped 293 // another read request that will downgrade our exclusive block 294 // to shared 295 if (inService && 296 (!deferredTargets.empty() || hasPostInvalidate() || 297 (pkt->needsExclusive() && 298 (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 299 // need to put on deferred list 300 if (hasPostInvalidate()) 301 replaceUpgrade(pkt); 302 deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true); 303 } else { 304 // No request outstanding, or still OK to append to 305 // outstanding request: append to regular target list. Only 306 // mark pending if current request hasn't been issued yet 307 // (isn't in service). 308 targets.add(pkt, whenReady, _order, Target::FromCPU, !inService); 309 } 310} 311 312bool 313MSHR::handleSnoop(PacketPtr pkt, Counter _order) 314{ 315 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 316 pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 317 if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 318 // Request has not been issued yet, or it's been issued 319 // locally but is buffered unissued at some downstream cache 320 // which is forwarding us this snoop. Either way, the packet 321 // we're snooping logically precedes this MSHR's request, so 322 // the snoop has no impact on the MSHR, but must be processed 323 // in the standard way by the cache. The only exception is 324 // that if we're an L2+ cache buffering an UpgradeReq from a 325 // higher-level cache, and the snoop is invalidating, then our 326 // buffered upgrades must be converted to read exclusives, 327 // since the upper-level cache no longer has a valid copy. 328 // That is, even though the upper-level cache got out on its 329 // local bus first, some other invalidating transaction 330 // reached the global bus before the upgrade did. 331 if (pkt->needsExclusive()) { 332 targets.replaceUpgrades(); 333 deferredTargets.replaceUpgrades(); 334 } 335 336 return false; 337 } 338 339 // From here on down, the request issued by this MSHR logically 340 // precedes the request we're snooping. 341 if (pkt->needsExclusive()) { 342 // snooped request still precedes the re-request we'll have to 343 // issue for deferred targets, if any... 344 deferredTargets.replaceUpgrades(); 345 } 346 347 if (hasPostInvalidate()) { 348 // a prior snoop has already appended an invalidation, so 349 // logically we don't have the block anymore; no need for 350 // further snooping. 351 return true; 352 } 353 354 if (isPendingDirty() || pkt->isInvalidate()) { 355 // We need to save and replay the packet in two cases: 356 // 1. We're awaiting an exclusive copy, so ownership is pending, 357 // and we need to respond after we receive data. 358 // 2. It's an invalidation (e.g., UpgradeReq), and we need 359 // to forward the snoop up the hierarchy after the current 360 // transaction completes. 361 362 // Actual target device (typ. a memory) will delete the 363 // packet on reception, so we need to save a copy here. 364 365 // Clear flags and also allocate new data as the original 366 // packet data storage may have been deleted by the time we 367 // get to send this packet. 368 PacketPtr cp_pkt = nullptr; 369 370 if (isPendingDirty()) { 371 // Case 1: The new packet will need to get the response from the 372 // MSHR already queued up here 373 cp_pkt = new Packet(pkt, true, true); 374 pkt->assertMemInhibit(); 375 // in the case of an uncacheable request there is no need 376 // to set the exclusive flag, but since the recipient does 377 // not care there is no harm in doing so 378 pkt->setSupplyExclusive(); 379 } else { 380 // Case 2: We only need to buffer the packet for information 381 // purposes; the original request can proceed without waiting 382 // => Create a copy of the request, as that may get deallocated as 383 // well 384 cp_pkt = new Packet(new Request(*pkt->req), pkt->cmd); 385 DPRINTF(Cache, "Copying packet %p -> %p and request %p -> %p\n", 386 pkt, cp_pkt, pkt->req, cp_pkt->req); 387 } 388 targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 389 downstreamPending && targets.needsExclusive); 390 391 if (pkt->needsExclusive()) { 392 // This transaction will take away our pending copy 393 postInvalidate = true; 394 } 395 } 396 397 if (!pkt->needsExclusive() && !pkt->req->isUncacheable()) { 398 // This transaction will get a read-shared copy, downgrading 399 // our copy if we had an exclusive one 400 postDowngrade = true; 401 pkt->assertShared(); 402 } 403 404 return true; 405} 406 407 408bool 409MSHR::promoteDeferredTargets() 410{ 411 assert(targets.empty()); 412 if (deferredTargets.empty()) { 413 return false; 414 } 415 416 // swap targets & deferredTargets lists 417 std::swap(targets, deferredTargets); 418 419 // clear deferredTargets flags 420 deferredTargets.resetFlags(); 421 422 order = targets.front().order; 423 readyTime = std::max(curTick(), targets.front().readyTime); 424 425 return true; 426} 427 428 429void 430MSHR::handleFill(PacketPtr pkt, CacheBlk *blk) 431{ 432 if (!pkt->sharedAsserted() 433 && !(hasPostInvalidate() || hasPostDowngrade()) 434 && deferredTargets.needsExclusive) { 435 // We got an exclusive response, but we have deferred targets 436 // which are waiting to request an exclusive copy (not because 437 // of a pending invalidate). This can happen if the original 438 // request was for a read-only (non-exclusive) block, but we 439 // got an exclusive copy anyway because of the E part of the 440 // MOESI/MESI protocol. Since we got the exclusive copy 441 // there's no need to defer the targets, so move them up to 442 // the regular target list. 443 assert(!targets.needsExclusive); 444 targets.needsExclusive = true; 445 // if any of the deferred targets were upper-level cache 446 // requests marked downstreamPending, need to clear that 447 assert(!downstreamPending); // not pending here anymore 448 deferredTargets.clearDownstreamPending(); 449 // this clears out deferredTargets too 450 targets.splice(targets.end(), deferredTargets); 451 deferredTargets.resetFlags(); 452 } 453} 454 455 456bool 457MSHR::checkFunctional(PacketPtr pkt) 458{ 459 // For printing, we treat the MSHR as a whole as single entity. 460 // For other requests, we iterate over the individual targets 461 // since that's where the actual data lies. 462 if (pkt->isPrint()) { 463 pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL); 464 return false; 465 } else { 466 return (targets.checkFunctional(pkt) || 467 deferredTargets.checkFunctional(pkt)); 468 } 469} 470 471 472void 473MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 474{ 475 ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n", 476 prefix, blkAddr, blkAddr + blkSize - 1, 477 isSecure ? "s" : "ns", 478 isForward ? "Forward" : "", 479 isForwardNoResponse() ? "ForwNoResp" : "", 480 needsExclusive() ? "Excl" : "", 481 _isUncacheable ? "Unc" : "", 482 inService ? "InSvc" : "", 483 downstreamPending ? "DwnPend" : "", 484 hasPostInvalidate() ? "PostInv" : "", 485 hasPostDowngrade() ? "PostDowngr" : ""); 486 487 ccprintf(os, "%s Targets:\n", prefix); 488 targets.print(os, verbosity, prefix + " "); 489 if (!deferredTargets.empty()) { 490 ccprintf(os, "%s Deferred Targets:\n", prefix); 491 deferredTargets.print(os, verbosity, prefix + " "); 492 } 493} 494 495std::string 496MSHR::print() const 497{ 498 ostringstream str; 499 print(str); 500 return str.str(); 501} 502