cache.hh revision 9445:5963165c00cb
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __CACHE_HH__ 53#define __CACHE_HH__ 54 55#include "base/misc.hh" // fatal, panic, and warn 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/mshr.hh" 59#include "sim/eventq.hh" 60 61//Forward decleration 62class BasePrefetcher; 63 64/** 65 * A template-policy based cache. The behavior of the cache can be altered by 66 * supplying different template policies. TagStore handles all tag and data 67 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 68 */ 69template <class TagStore> 70class Cache : public BaseCache 71{ 72 public: 73 /** Define the type of cache block to use. */ 74 typedef typename TagStore::BlkType BlkType; 75 /** A typedef for a list of BlkType pointers. */ 76 typedef typename TagStore::BlkList BlkList; 77 78 protected: 79 typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor; 80 81 /** 82 * The CPU-side port extends the base cache slave port with access 83 * functions for functional, atomic and timing requests. 84 */ 85 class CpuSidePort : public CacheSlavePort 86 { 87 private: 88 89 // a pointer to our specific cache implementation 90 Cache<TagStore> *cache; 91 92 protected: 93 94 virtual bool recvTimingSnoopResp(PacketPtr pkt); 95 96 virtual bool recvTimingReq(PacketPtr pkt); 97 98 virtual Tick recvAtomic(PacketPtr pkt); 99 100 virtual void recvFunctional(PacketPtr pkt); 101 102 virtual unsigned deviceBlockSize() const 103 { return cache->getBlockSize(); } 104 105 virtual AddrRangeList getAddrRanges() const; 106 107 public: 108 109 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 110 const std::string &_label); 111 112 }; 113 114 /** 115 * Override the default behaviour of sendDeferredPacket to enable 116 * the memory-side cache port to also send requests based on the 117 * current MSHR status. This queue has a pointer to our specific 118 * cache implementation and is used by the MemSidePort. 119 */ 120 class MemSidePacketQueue : public MasterPacketQueue 121 { 122 123 protected: 124 125 Cache<TagStore> &cache; 126 127 public: 128 129 MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port, 130 const std::string &label) : 131 MasterPacketQueue(cache, port, label), cache(cache) { } 132 133 /** 134 * Override the normal sendDeferredPacket and do not only 135 * consider the transmit list (used for responses), but also 136 * requests. 137 */ 138 virtual void sendDeferredPacket(); 139 140 }; 141 142 /** 143 * The memory-side port extends the base cache master port with 144 * access functions for functional, atomic and timing snoops. 145 */ 146 class MemSidePort : public CacheMasterPort 147 { 148 private: 149 150 /** The cache-specific queue. */ 151 MemSidePacketQueue _queue; 152 153 // a pointer to our specific cache implementation 154 Cache<TagStore> *cache; 155 156 protected: 157 158 virtual void recvTimingSnoopReq(PacketPtr pkt); 159 160 virtual bool recvTimingResp(PacketPtr pkt); 161 162 virtual Tick recvAtomicSnoop(PacketPtr pkt); 163 164 virtual void recvFunctionalSnoop(PacketPtr pkt); 165 166 virtual unsigned deviceBlockSize() const 167 { return cache->getBlockSize(); } 168 169 public: 170 171 MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 172 const std::string &_label); 173 }; 174 175 /** Tag and data Storage */ 176 TagStore *tags; 177 178 /** Prefetcher */ 179 BasePrefetcher *prefetcher; 180 181 /** Temporary cache block for occasional transitory use */ 182 BlkType *tempBlock; 183 184 /** 185 * This cache should allocate a block on a line-sized write miss. 186 */ 187 const bool doFastWrites; 188 189 /** 190 * Notify the prefetcher on every access, not just misses. 191 */ 192 const bool prefetchOnAccess; 193 194 /** 195 * @todo this is a temporary workaround until the 4-phase code is committed. 196 * upstream caches need this packet until true is returned, so hold it for 197 * deletion until a subsequent call 198 */ 199 std::vector<PacketPtr> pendingDelete; 200 201 /** 202 * Does all the processing necessary to perform the provided request. 203 * @param pkt The memory request to perform. 204 * @param lat The latency of the access. 205 * @param writebacks List for any writebacks that need to be performed. 206 * @param update True if the replacement data should be updated. 207 * @return Boolean indicating whether the request was satisfied. 208 */ 209 bool access(PacketPtr pkt, BlkType *&blk, 210 Cycles &lat, PacketList &writebacks); 211 212 /** 213 *Handle doing the Compare and Swap function for SPARC. 214 */ 215 void cmpAndSwap(BlkType *blk, PacketPtr pkt); 216 217 /** 218 * Find a block frame for new block at address addr, assuming that 219 * the block is not currently in the cache. Append writebacks if 220 * any to provided packet list. Return free block frame. May 221 * return NULL if there are no replaceable blocks at the moment. 222 */ 223 BlkType *allocateBlock(Addr addr, PacketList &writebacks); 224 225 /** 226 * Populates a cache block and handles all outstanding requests for the 227 * satisfied fill request. This version takes two memory requests. One 228 * contains the fill data, the other is an optional target to satisfy. 229 * @param pkt The memory request with the fill data. 230 * @param blk The cache block if it already exists. 231 * @param writebacks List for any writebacks that need to be performed. 232 * @return Pointer to the new cache block. 233 */ 234 BlkType *handleFill(PacketPtr pkt, BlkType *blk, 235 PacketList &writebacks); 236 237 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 238 bool deferred_response = false, 239 bool pending_downgrade = false); 240 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 241 242 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 243 bool already_copied, bool pending_inval); 244 245 /** 246 * Sets the blk to the new state. 247 * @param blk The cache block being snooped. 248 * @param new_state The new coherence state for the block. 249 */ 250 void handleSnoop(PacketPtr ptk, BlkType *blk, 251 bool is_timing, bool is_deferred, bool pending_inval); 252 253 /** 254 * Create a writeback request for the given block. 255 * @param blk The block to writeback. 256 * @return The writeback request for the block. 257 */ 258 PacketPtr writebackBlk(BlkType *blk); 259 260 261 void memWriteback(); 262 void memInvalidate(); 263 bool isDirty() const; 264 265 /** 266 * Cache block visitor that writes back dirty cache blocks using 267 * functional writes. 268 * 269 * \return Always returns true. 270 */ 271 bool writebackVisitor(BlkType &blk); 272 /** 273 * Cache block visitor that invalidates all blocks in the cache. 274 * 275 * @warn Dirty cache lines will not be written back to memory. 276 * 277 * \return Always returns true. 278 */ 279 bool invalidateVisitor(BlkType &blk); 280 281 /** 282 * Flush a cache line due to an uncacheable memory access to the 283 * line. 284 * 285 * @note This shouldn't normally happen, but we need to handle it 286 * since some architecture models don't implement cache 287 * maintenance operations. We won't even try to get a decent 288 * timing here since the line should have been flushed earlier by 289 * a cache maintenance operation. 290 */ 291 void uncacheableFlush(PacketPtr pkt); 292 293 public: 294 /** Instantiates a basic cache object. */ 295 Cache(const Params *p, TagStore *tags); 296 297 void regStats(); 298 299 /** 300 * Performs the access specified by the request. 301 * @param pkt The request to perform. 302 * @return The result of the access. 303 */ 304 bool timingAccess(PacketPtr pkt); 305 306 /** 307 * Performs the access specified by the request. 308 * @param pkt The request to perform. 309 * @return The number of ticks required for the access. 310 */ 311 Tick atomicAccess(PacketPtr pkt); 312 313 /** 314 * Performs the access specified by the request. 315 * @param pkt The request to perform. 316 * @param fromCpuSide from the CPU side port or the memory side port 317 */ 318 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 319 320 /** 321 * Handles a response (cache line fill/write ack) from the bus. 322 * @param pkt The request being responded to. 323 */ 324 void handleResponse(PacketPtr pkt); 325 326 /** 327 * Snoops bus transactions to maintain coherence. 328 * @param pkt The current bus transaction. 329 */ 330 void snoopTiming(PacketPtr pkt); 331 332 /** 333 * Snoop for the provided request in the cache and return the estimated 334 * time of completion. 335 * @param pkt The memory request to snoop 336 * @return The number of cycles required for the snoop. 337 */ 338 Cycles snoopAtomic(PacketPtr pkt); 339 340 /** 341 * Squash all requests associated with specified thread. 342 * intended for use by I-cache. 343 * @param threadNum The thread to squash. 344 */ 345 void squash(int threadNum); 346 347 /** 348 * Generate an appropriate downstream bus request packet for the 349 * given parameters. 350 * @param cpu_pkt The upstream request that needs to be satisfied. 351 * @param blk The block currently in the cache corresponding to 352 * cpu_pkt (NULL if none). 353 * @param needsExclusive Indicates that an exclusive copy is required 354 * even if the request in cpu_pkt doesn't indicate that. 355 * @return A new Packet containing the request, or NULL if the 356 * current request in cpu_pkt should just be forwarded on. 357 */ 358 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 359 bool needsExclusive); 360 361 /** 362 * Return the next MSHR to service, either a pending miss from the 363 * mshrQueue, a buffered write from the write buffer, or something 364 * from the prefetcher. This function is responsible for 365 * prioritizing among those sources on the fly. 366 */ 367 MSHR *getNextMSHR(); 368 369 /** 370 * Selects an outstanding request to service. Called when the 371 * cache gets granted the downstream bus in timing mode. 372 * @return The request to service, NULL if none found. 373 */ 374 PacketPtr getTimingPacket(); 375 376 /** 377 * Marks a request as in service (sent on the bus). This can have side 378 * effect since storage for no response commands is deallocated once they 379 * are successfully sent. 380 * @param pkt The request that was sent on the bus. 381 */ 382 void markInService(MSHR *mshr, PacketPtr pkt = 0); 383 384 /** 385 * Return whether there are any outstanding misses. 386 */ 387 bool outstandingMisses() const 388 { 389 return mshrQueue.allocated != 0; 390 } 391 392 CacheBlk *findBlock(Addr addr) { 393 return tags->findBlock(addr); 394 } 395 396 bool inCache(Addr addr) { 397 return (tags->findBlock(addr) != 0); 398 } 399 400 bool inMissQueue(Addr addr) { 401 return (mshrQueue.findMatch(addr) != 0); 402 } 403 404 /** 405 * Find next request ready time from among possible sources. 406 */ 407 Tick nextMSHRReadyTime(); 408 409 /** serialize the state of the caches 410 * We currently don't support checkpointing cache state, so this panics. 411 */ 412 virtual void serialize(std::ostream &os); 413 void unserialize(Checkpoint *cp, const std::string §ion); 414}; 415 416#endif // __CACHE_HH__ 417