cache.hh revision 8702:2764cd55d2ad
13855Sbinkertn@umich.edu/* 23855Sbinkertn@umich.edu * Copyright (c) 2012 ARM Limited 33855Sbinkertn@umich.edu * All rights reserved. 43855Sbinkertn@umich.edu * 53855Sbinkertn@umich.edu * The license below extends only to copyright in the software and shall 63855Sbinkertn@umich.edu * not be construed as granting a license to any other intellectual 73855Sbinkertn@umich.edu * property including but not limited to intellectual property relating 83855Sbinkertn@umich.edu * to a hardware implementation of the functionality of the software 93855Sbinkertn@umich.edu * licensed hereunder. You may use the software subject to the license 103855Sbinkertn@umich.edu * terms below provided that you ensure that this notice is replicated 113855Sbinkertn@umich.edu * unmodified and in its entirety in all distributions of the software, 123855Sbinkertn@umich.edu * modified or unmodified, in source code or in binary form. 133855Sbinkertn@umich.edu * 143855Sbinkertn@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 153855Sbinkertn@umich.edu * All rights reserved. 163855Sbinkertn@umich.edu * 173855Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 183855Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 193855Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 203855Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 213855Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 223855Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 233855Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 243855Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 253855Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 263855Sbinkertn@umich.edu * this software without specific prior written permission. 273855Sbinkertn@umich.edu * 283855Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293855Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303855Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313855Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323855Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333855Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343855Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353855Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363855Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373855Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383855Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393855Sbinkertn@umich.edu * 403855Sbinkertn@umich.edu * Authors: Erik Hallnor 413855Sbinkertn@umich.edu * Dave Greene 423855Sbinkertn@umich.edu * Steve Reinhardt 433855Sbinkertn@umich.edu * Ron Dreslinski 443855Sbinkertn@umich.edu */ 453855Sbinkertn@umich.edu 463855Sbinkertn@umich.edu/** 473855Sbinkertn@umich.edu * @file 483855Sbinkertn@umich.edu * Describes a cache based on template policies. 493855Sbinkertn@umich.edu */ 503855Sbinkertn@umich.edu 513855Sbinkertn@umich.edu#ifndef __CACHE_HH__ 523855Sbinkertn@umich.edu#define __CACHE_HH__ 533855Sbinkertn@umich.edu 543855Sbinkertn@umich.edu#include "base/misc.hh" // fatal, panic, and warn 553855Sbinkertn@umich.edu#include "mem/cache/base.hh" 563855Sbinkertn@umich.edu#include "mem/cache/blk.hh" 573855Sbinkertn@umich.edu#include "mem/cache/mshr.hh" 583855Sbinkertn@umich.edu#include "sim/eventq.hh" 593855Sbinkertn@umich.edu 603855Sbinkertn@umich.edu//Forward decleration 613855Sbinkertn@umich.educlass BasePrefetcher; 623855Sbinkertn@umich.edu 633855Sbinkertn@umich.edu/** 643855Sbinkertn@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 653855Sbinkertn@umich.edu * supplying different template policies. TagStore handles all tag and data 663855Sbinkertn@umich.edu * storage @sa TagStore. 673855Sbinkertn@umich.edu */ 683855Sbinkertn@umich.edutemplate <class TagStore> 693855Sbinkertn@umich.educlass Cache : public BaseCache 703855Sbinkertn@umich.edu{ 713855Sbinkertn@umich.edu public: 723855Sbinkertn@umich.edu /** Define the type of cache block to use. */ 733855Sbinkertn@umich.edu typedef typename TagStore::BlkType BlkType; 743855Sbinkertn@umich.edu /** A typedef for a list of BlkType pointers. */ 753855Sbinkertn@umich.edu typedef typename TagStore::BlkList BlkList; 763855Sbinkertn@umich.edu 773855Sbinkertn@umich.edu protected: 783855Sbinkertn@umich.edu 793855Sbinkertn@umich.edu class CpuSidePort : public CachePort 803855Sbinkertn@umich.edu { 813855Sbinkertn@umich.edu public: 823855Sbinkertn@umich.edu CpuSidePort(const std::string &_name, 833855Sbinkertn@umich.edu Cache<TagStore> *_cache, 843855Sbinkertn@umich.edu const std::string &_label); 853855Sbinkertn@umich.edu 863855Sbinkertn@umich.edu // BaseCache::CachePort just has a BaseCache *; this function 873855Sbinkertn@umich.edu // lets us get back the type info we lost when we stored the 883855Sbinkertn@umich.edu // cache pointer there. 893855Sbinkertn@umich.edu Cache<TagStore> *myCache() { 903855Sbinkertn@umich.edu return static_cast<Cache<TagStore> *>(cache); 913855Sbinkertn@umich.edu } 923855Sbinkertn@umich.edu 933855Sbinkertn@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 943855Sbinkertn@umich.edu bool &snoop); 953855Sbinkertn@umich.edu 963855Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 973855Sbinkertn@umich.edu 983855Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 993855Sbinkertn@umich.edu 1003855Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 1013855Sbinkertn@umich.edu }; 1023855Sbinkertn@umich.edu 1033855Sbinkertn@umich.edu class MemSidePort : public CachePort 1043855Sbinkertn@umich.edu { 1053855Sbinkertn@umich.edu public: 1063855Sbinkertn@umich.edu MemSidePort(const std::string &_name, 1073855Sbinkertn@umich.edu Cache<TagStore> *_cache, 1083855Sbinkertn@umich.edu const std::string &_label); 1093855Sbinkertn@umich.edu 1103855Sbinkertn@umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1113855Sbinkertn@umich.edu // lets us get back the type info we lost when we stored the 1123855Sbinkertn@umich.edu // cache pointer there. 1133855Sbinkertn@umich.edu Cache<TagStore> *myCache() { 1143855Sbinkertn@umich.edu return static_cast<Cache<TagStore> *>(cache); 1153855Sbinkertn@umich.edu } 1163855Sbinkertn@umich.edu 1173855Sbinkertn@umich.edu void sendPacket(); 1183855Sbinkertn@umich.edu 1193855Sbinkertn@umich.edu void processSendEvent(); 1203855Sbinkertn@umich.edu 1213855Sbinkertn@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1223855Sbinkertn@umich.edu bool &snoop); 1233855Sbinkertn@umich.edu 1243855Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1253855Sbinkertn@umich.edu 1263855Sbinkertn@umich.edu virtual void recvRetry(); 1273855Sbinkertn@umich.edu 1283855Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1293855Sbinkertn@umich.edu 1303855Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 1313855Sbinkertn@umich.edu 1323855Sbinkertn@umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 1333855Sbinkertn@umich.edu SendEvent; 1343855Sbinkertn@umich.edu }; 1353855Sbinkertn@umich.edu 1363855Sbinkertn@umich.edu /** Tag and data Storage */ 1373855Sbinkertn@umich.edu TagStore *tags; 1383855Sbinkertn@umich.edu 1393855Sbinkertn@umich.edu /** Prefetcher */ 1403855Sbinkertn@umich.edu BasePrefetcher *prefetcher; 1413855Sbinkertn@umich.edu 1423855Sbinkertn@umich.edu /** Temporary cache block for occasional transitory use */ 1433855Sbinkertn@umich.edu BlkType *tempBlock; 1443855Sbinkertn@umich.edu 1453855Sbinkertn@umich.edu /** 1463855Sbinkertn@umich.edu * This cache should allocate a block on a line-sized write miss. 1473855Sbinkertn@umich.edu */ 1483855Sbinkertn@umich.edu const bool doFastWrites; 1493855Sbinkertn@umich.edu 1503855Sbinkertn@umich.edu /** 1513855Sbinkertn@umich.edu * Notify the prefetcher on every access, not just misses. 1523855Sbinkertn@umich.edu */ 1533855Sbinkertn@umich.edu const bool prefetchOnAccess; 1543855Sbinkertn@umich.edu 1553855Sbinkertn@umich.edu /** 1563855Sbinkertn@umich.edu * Does all the processing necessary to perform the provided request. 1573855Sbinkertn@umich.edu * @param pkt The memory request to perform. 1583855Sbinkertn@umich.edu * @param lat The latency of the access. 1593855Sbinkertn@umich.edu * @param writebacks List for any writebacks that need to be performed. 1603855Sbinkertn@umich.edu * @param update True if the replacement data should be updated. 1613855Sbinkertn@umich.edu * @return Boolean indicating whether the request was satisfied. 1623855Sbinkertn@umich.edu */ 1633855Sbinkertn@umich.edu bool access(PacketPtr pkt, BlkType *&blk, 1643855Sbinkertn@umich.edu int &lat, PacketList &writebacks); 1653855Sbinkertn@umich.edu 1663855Sbinkertn@umich.edu /** 1673855Sbinkertn@umich.edu *Handle doing the Compare and Swap function for SPARC. 1683855Sbinkertn@umich.edu */ 1693855Sbinkertn@umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1703855Sbinkertn@umich.edu 1713855Sbinkertn@umich.edu /** 1723855Sbinkertn@umich.edu * Find a block frame for new block at address addr, assuming that 1733855Sbinkertn@umich.edu * the block is not currently in the cache. Append writebacks if 1743855Sbinkertn@umich.edu * any to provided packet list. Return free block frame. May 1753855Sbinkertn@umich.edu * return NULL if there are no replaceable blocks at the moment. 1763855Sbinkertn@umich.edu */ 1773855Sbinkertn@umich.edu BlkType *allocateBlock(Addr addr, PacketList &writebacks); 1783855Sbinkertn@umich.edu 1793855Sbinkertn@umich.edu /** 1803855Sbinkertn@umich.edu * Populates a cache block and handles all outstanding requests for the 1813855Sbinkertn@umich.edu * satisfied fill request. This version takes two memory requests. One 1823855Sbinkertn@umich.edu * contains the fill data, the other is an optional target to satisfy. 1833855Sbinkertn@umich.edu * @param pkt The memory request with the fill data. 1843855Sbinkertn@umich.edu * @param blk The cache block if it already exists. 1853855Sbinkertn@umich.edu * @param writebacks List for any writebacks that need to be performed. 1863855Sbinkertn@umich.edu * @return Pointer to the new cache block. 1873855Sbinkertn@umich.edu */ 1883855Sbinkertn@umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1893855Sbinkertn@umich.edu PacketList &writebacks); 1903855Sbinkertn@umich.edu 1913855Sbinkertn@umich.edu void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 1923855Sbinkertn@umich.edu bool deferred_response = false, 1933855Sbinkertn@umich.edu bool pending_downgrade = false); 1943855Sbinkertn@umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 1953855Sbinkertn@umich.edu 1963855Sbinkertn@umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 1973855Sbinkertn@umich.edu bool already_copied, bool pending_inval); 1983855Sbinkertn@umich.edu 1993855Sbinkertn@umich.edu /** 2003855Sbinkertn@umich.edu * Sets the blk to the new state. 2013855Sbinkertn@umich.edu * @param blk The cache block being snooped. 2023855Sbinkertn@umich.edu * @param new_state The new coherence state for the block. 2033855Sbinkertn@umich.edu */ 2043855Sbinkertn@umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 2053855Sbinkertn@umich.edu bool is_timing, bool is_deferred, bool pending_inval); 2063855Sbinkertn@umich.edu 2073855Sbinkertn@umich.edu /** 2083855Sbinkertn@umich.edu * Create a writeback request for the given block. 2093855Sbinkertn@umich.edu * @param blk The block to writeback. 2103855Sbinkertn@umich.edu * @return The writeback request for the block. 2113855Sbinkertn@umich.edu */ 2123855Sbinkertn@umich.edu PacketPtr writebackBlk(BlkType *blk); 2133855Sbinkertn@umich.edu 2143855Sbinkertn@umich.edu public: 2153855Sbinkertn@umich.edu /** Instantiates a basic cache object. */ 2163855Sbinkertn@umich.edu Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher); 2173855Sbinkertn@umich.edu 2183855Sbinkertn@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2193855Sbinkertn@umich.edu virtual void deletePortRefs(Port *p); 2203855Sbinkertn@umich.edu 2213855Sbinkertn@umich.edu void regStats(); 2223855Sbinkertn@umich.edu 2233855Sbinkertn@umich.edu /** 2243855Sbinkertn@umich.edu * Performs the access specified by the request. 2253855Sbinkertn@umich.edu * @param pkt The request to perform. 2263855Sbinkertn@umich.edu * @return The result of the access. 2273855Sbinkertn@umich.edu */ 2283855Sbinkertn@umich.edu bool timingAccess(PacketPtr pkt); 2293855Sbinkertn@umich.edu 2303855Sbinkertn@umich.edu /** 2313855Sbinkertn@umich.edu * Performs the access specified by the request. 2323855Sbinkertn@umich.edu * @param pkt The request to perform. 2333855Sbinkertn@umich.edu * @return The result of the access. 2343855Sbinkertn@umich.edu */ 2353855Sbinkertn@umich.edu Tick atomicAccess(PacketPtr pkt); 2363855Sbinkertn@umich.edu 2373855Sbinkertn@umich.edu /** 2383855Sbinkertn@umich.edu * Performs the access specified by the request. 2393855Sbinkertn@umich.edu * @param pkt The request to perform. 2403855Sbinkertn@umich.edu * @param fromCpuSide from the CPU side port or the memory side port 2413855Sbinkertn@umich.edu */ 2423855Sbinkertn@umich.edu void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2433855Sbinkertn@umich.edu 2443855Sbinkertn@umich.edu /** 2453855Sbinkertn@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2463855Sbinkertn@umich.edu * @param pkt The request being responded to. 2473855Sbinkertn@umich.edu */ 2483855Sbinkertn@umich.edu void handleResponse(PacketPtr pkt); 2493855Sbinkertn@umich.edu 2503855Sbinkertn@umich.edu /** 2513855Sbinkertn@umich.edu * Snoops bus transactions to maintain coherence. 2523855Sbinkertn@umich.edu * @param pkt The current bus transaction. 2533855Sbinkertn@umich.edu */ 2543855Sbinkertn@umich.edu void snoopTiming(PacketPtr pkt); 2553855Sbinkertn@umich.edu 2563855Sbinkertn@umich.edu /** 2573855Sbinkertn@umich.edu * Snoop for the provided request in the cache and return the estimated 2583855Sbinkertn@umich.edu * time of completion. 2593855Sbinkertn@umich.edu * @param pkt The memory request to snoop 2603855Sbinkertn@umich.edu * @return The estimated completion time. 2613855Sbinkertn@umich.edu */ 2623855Sbinkertn@umich.edu Tick snoopAtomic(PacketPtr pkt); 2633855Sbinkertn@umich.edu 2643855Sbinkertn@umich.edu /** 2653855Sbinkertn@umich.edu * Squash all requests associated with specified thread. 2663855Sbinkertn@umich.edu * intended for use by I-cache. 2673855Sbinkertn@umich.edu * @param threadNum The thread to squash. 2683855Sbinkertn@umich.edu */ 2693855Sbinkertn@umich.edu void squash(int threadNum); 2703855Sbinkertn@umich.edu 2713855Sbinkertn@umich.edu /** 2723855Sbinkertn@umich.edu * Generate an appropriate downstream bus request packet for the 2733855Sbinkertn@umich.edu * given parameters. 2743855Sbinkertn@umich.edu * @param cpu_pkt The upstream request that needs to be satisfied. 2753855Sbinkertn@umich.edu * @param blk The block currently in the cache corresponding to 2763855Sbinkertn@umich.edu * cpu_pkt (NULL if none). 2773855Sbinkertn@umich.edu * @param needsExclusive Indicates that an exclusive copy is required 2783855Sbinkertn@umich.edu * even if the request in cpu_pkt doesn't indicate that. 2793855Sbinkertn@umich.edu * @return A new Packet containing the request, or NULL if the 2803855Sbinkertn@umich.edu * current request in cpu_pkt should just be forwarded on. 2813855Sbinkertn@umich.edu */ 2823855Sbinkertn@umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2833855Sbinkertn@umich.edu bool needsExclusive); 2843855Sbinkertn@umich.edu 2853855Sbinkertn@umich.edu /** 2863855Sbinkertn@umich.edu * Return the next MSHR to service, either a pending miss from the 2873855Sbinkertn@umich.edu * mshrQueue, a buffered write from the write buffer, or something 2883855Sbinkertn@umich.edu * from the prefetcher. This function is responsible for 2893855Sbinkertn@umich.edu * prioritizing among those sources on the fly. 2903855Sbinkertn@umich.edu */ 2913855Sbinkertn@umich.edu MSHR *getNextMSHR(); 2923855Sbinkertn@umich.edu 2933855Sbinkertn@umich.edu /** 2943855Sbinkertn@umich.edu * Selects an outstanding request to service. Called when the 2953855Sbinkertn@umich.edu * cache gets granted the downstream bus in timing mode. 2963855Sbinkertn@umich.edu * @return The request to service, NULL if none found. 2973855Sbinkertn@umich.edu */ 2983855Sbinkertn@umich.edu PacketPtr getTimingPacket(); 2993855Sbinkertn@umich.edu 3003855Sbinkertn@umich.edu /** 3013855Sbinkertn@umich.edu * Marks a request as in service (sent on the bus). This can have side 3023855Sbinkertn@umich.edu * effect since storage for no response commands is deallocated once they 3033855Sbinkertn@umich.edu * are successfully sent. 3043855Sbinkertn@umich.edu * @param pkt The request that was sent on the bus. 3053855Sbinkertn@umich.edu */ 3063855Sbinkertn@umich.edu void markInService(MSHR *mshr, PacketPtr pkt = 0); 3073855Sbinkertn@umich.edu 3083855Sbinkertn@umich.edu /** 3093855Sbinkertn@umich.edu * Perform the given writeback request. 3103855Sbinkertn@umich.edu * @param pkt The writeback request. 3113855Sbinkertn@umich.edu */ 3123855Sbinkertn@umich.edu void doWriteback(PacketPtr pkt); 3133855Sbinkertn@umich.edu 3143855Sbinkertn@umich.edu /** 3153855Sbinkertn@umich.edu * Return whether there are any outstanding misses. 3163855Sbinkertn@umich.edu */ 3173855Sbinkertn@umich.edu bool outstandingMisses() const 3183855Sbinkertn@umich.edu { 3193855Sbinkertn@umich.edu return mshrQueue.allocated != 0; 3203855Sbinkertn@umich.edu } 3213855Sbinkertn@umich.edu 3223855Sbinkertn@umich.edu CacheBlk *findBlock(Addr addr) { 3233855Sbinkertn@umich.edu return tags->findBlock(addr); 324 } 325 326 bool inCache(Addr addr) { 327 return (tags->findBlock(addr) != 0); 328 } 329 330 bool inMissQueue(Addr addr) { 331 return (mshrQueue.findMatch(addr) != 0); 332 } 333 334 /** 335 * Find next request ready time from among possible sources. 336 */ 337 Tick nextMSHRReadyTime(); 338}; 339 340#endif // __CACHE_HH__ 341