cache.hh revision 5707:da86e00f87a0
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Dave Greene 30 * Steve Reinhardt 31 * Ron Dreslinski 32 */ 33 34/** 35 * @file 36 * Describes a cache based on template policies. 37 */ 38 39#ifndef __CACHE_HH__ 40#define __CACHE_HH__ 41 42#include "base/misc.hh" // fatal, panic, and warn 43 44#include "mem/cache/base.hh" 45#include "mem/cache/blk.hh" 46#include "mem/cache/mshr.hh" 47 48#include "sim/eventq.hh" 49 50//Forward decleration 51class BasePrefetcher; 52 53/** 54 * A template-policy based cache. The behavior of the cache can be altered by 55 * supplying different template policies. TagStore handles all tag and data 56 * storage @sa TagStore. 57 */ 58template <class TagStore> 59class Cache : public BaseCache 60{ 61 public: 62 /** Define the type of cache block to use. */ 63 typedef typename TagStore::BlkType BlkType; 64 /** A typedef for a list of BlkType pointers. */ 65 typedef typename TagStore::BlkList BlkList; 66 67 bool prefetchAccess; 68 69 protected: 70 71 class CpuSidePort : public CachePort 72 { 73 public: 74 CpuSidePort(const std::string &_name, 75 Cache<TagStore> *_cache, 76 const std::string &_label, 77 std::vector<Range<Addr> > filterRanges); 78 79 // BaseCache::CachePort just has a BaseCache *; this function 80 // lets us get back the type info we lost when we stored the 81 // cache pointer there. 82 Cache<TagStore> *myCache() { 83 return static_cast<Cache<TagStore> *>(cache); 84 } 85 86 virtual void getDeviceAddressRanges(AddrRangeList &resp, 87 bool &snoop); 88 89 virtual bool recvTiming(PacketPtr pkt); 90 91 virtual Tick recvAtomic(PacketPtr pkt); 92 93 virtual void recvFunctional(PacketPtr pkt); 94 }; 95 96 class MemSidePort : public CachePort 97 { 98 public: 99 MemSidePort(const std::string &_name, 100 Cache<TagStore> *_cache, 101 const std::string &_label, 102 std::vector<Range<Addr> > filterRanges); 103 104 // BaseCache::CachePort just has a BaseCache *; this function 105 // lets us get back the type info we lost when we stored the 106 // cache pointer there. 107 Cache<TagStore> *myCache() { 108 return static_cast<Cache<TagStore> *>(cache); 109 } 110 111 void sendPacket(); 112 113 void processSendEvent(); 114 115 virtual void getDeviceAddressRanges(AddrRangeList &resp, 116 bool &snoop); 117 118 virtual bool recvTiming(PacketPtr pkt); 119 120 virtual void recvRetry(); 121 122 virtual Tick recvAtomic(PacketPtr pkt); 123 124 virtual void recvFunctional(PacketPtr pkt); 125 126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 127 SendEvent; 128 }; 129 130 /** Tag and data Storage */ 131 TagStore *tags; 132 133 /** Prefetcher */ 134 BasePrefetcher *prefetcher; 135 136 /** Temporary cache block for occasional transitory use */ 137 BlkType *tempBlock; 138 139 /** 140 * This cache should allocate a block on a line-sized write miss. 141 */ 142 const bool doFastWrites; 143 144 const bool prefetchMiss; 145 146 /** 147 * Does all the processing necessary to perform the provided request. 148 * @param pkt The memory request to perform. 149 * @param lat The latency of the access. 150 * @param writebacks List for any writebacks that need to be performed. 151 * @param update True if the replacement data should be updated. 152 * @return Boolean indicating whether the request was satisfied. 153 */ 154 bool access(PacketPtr pkt, BlkType *&blk, 155 int &lat, PacketList &writebacks); 156 157 /** 158 *Handle doing the Compare and Swap function for SPARC. 159 */ 160 void cmpAndSwap(BlkType *blk, PacketPtr pkt); 161 162 /** 163 * Find a block frame for new block at address addr, assuming that 164 * the block is not currently in the cache. Append writebacks if 165 * any to provided packet list. Return free block frame. May 166 * return NULL if there are no replaceable blocks at the moment. 167 */ 168 BlkType *allocateBlock(Addr addr, PacketList &writebacks); 169 170 /** 171 * Populates a cache block and handles all outstanding requests for the 172 * satisfied fill request. This version takes two memory requests. One 173 * contains the fill data, the other is an optional target to satisfy. 174 * @param pkt The memory request with the fill data. 175 * @param blk The cache block if it already exists. 176 * @param writebacks List for any writebacks that need to be performed. 177 * @return Pointer to the new cache block. 178 */ 179 BlkType *handleFill(PacketPtr pkt, BlkType *blk, 180 PacketList &writebacks); 181 182 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); 183 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 184 185 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 186 bool already_copied, bool pending_inval); 187 188 /** 189 * Sets the blk to the new state. 190 * @param blk The cache block being snooped. 191 * @param new_state The new coherence state for the block. 192 */ 193 void handleSnoop(PacketPtr ptk, BlkType *blk, 194 bool is_timing, bool is_deferred, bool pending_inval); 195 196 /** 197 * Create a writeback request for the given block. 198 * @param blk The block to writeback. 199 * @return The writeback request for the block. 200 */ 201 PacketPtr writebackBlk(BlkType *blk); 202 203 public: 204 /** Instantiates a basic cache object. */ 205 Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher); 206 207 virtual Port *getPort(const std::string &if_name, int idx = -1); 208 virtual void deletePortRefs(Port *p); 209 210 void regStats(); 211 212 /** 213 * Performs the access specified by the request. 214 * @param pkt The request to perform. 215 * @return The result of the access. 216 */ 217 bool timingAccess(PacketPtr pkt); 218 219 /** 220 * Performs the access specified by the request. 221 * @param pkt The request to perform. 222 * @return The result of the access. 223 */ 224 Tick atomicAccess(PacketPtr pkt); 225 226 /** 227 * Performs the access specified by the request. 228 * @param pkt The request to perform. 229 * @return The result of the access. 230 */ 231 void functionalAccess(PacketPtr pkt, CachePort *incomingPort, 232 CachePort *otherSidePort); 233 234 /** 235 * Handles a response (cache line fill/write ack) from the bus. 236 * @param pkt The request being responded to. 237 */ 238 void handleResponse(PacketPtr pkt); 239 240 /** 241 * Snoops bus transactions to maintain coherence. 242 * @param pkt The current bus transaction. 243 */ 244 void snoopTiming(PacketPtr pkt); 245 246 /** 247 * Snoop for the provided request in the cache and return the estimated 248 * time of completion. 249 * @param pkt The memory request to snoop 250 * @return The estimated completion time. 251 */ 252 Tick snoopAtomic(PacketPtr pkt); 253 254 /** 255 * Squash all requests associated with specified thread. 256 * intended for use by I-cache. 257 * @param threadNum The thread to squash. 258 */ 259 void squash(int threadNum); 260 261 /** 262 * Generate an appropriate downstream bus request packet for the 263 * given parameters. 264 * @param cpu_pkt The upstream request that needs to be satisfied. 265 * @param blk The block currently in the cache corresponding to 266 * cpu_pkt (NULL if none). 267 * @param needsExclusive Indicates that an exclusive copy is required 268 * even if the request in cpu_pkt doesn't indicate that. 269 * @return A new Packet containing the request, or NULL if the 270 * current request in cpu_pkt should just be forwarded on. 271 */ 272 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 273 bool needsExclusive); 274 275 /** 276 * Return the next MSHR to service, either a pending miss from the 277 * mshrQueue, a buffered write from the write buffer, or something 278 * from the prefetcher. This function is responsible for 279 * prioritizing among those sources on the fly. 280 */ 281 MSHR *getNextMSHR(); 282 283 /** 284 * Selects an outstanding request to service. Called when the 285 * cache gets granted the downstream bus in timing mode. 286 * @return The request to service, NULL if none found. 287 */ 288 PacketPtr getTimingPacket(); 289 290 /** 291 * Marks a request as in service (sent on the bus). This can have side 292 * effect since storage for no response commands is deallocated once they 293 * are successfully sent. 294 * @param pkt The request that was sent on the bus. 295 */ 296 void markInService(MSHR *mshr); 297 298 /** 299 * Perform the given writeback request. 300 * @param pkt The writeback request. 301 */ 302 void doWriteback(PacketPtr pkt); 303 304 /** 305 * Return whether there are any outstanding misses. 306 */ 307 bool outstandingMisses() const 308 { 309 return mshrQueue.allocated != 0; 310 } 311 312 CacheBlk *findBlock(Addr addr) { 313 return tags->findBlock(addr); 314 } 315 316 bool inCache(Addr addr) { 317 return (tags->findBlock(addr) != 0); 318 } 319 320 bool inMissQueue(Addr addr) { 321 return (mshrQueue.findMatch(addr) != 0); 322 } 323}; 324 325#endif // __CACHE_HH__ 326